The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.

Packet : 117143198dds.rar filelist
DDS\.sopc_builder\install.ptf
DDS\ADDER10B.vhd
DDS\ADDER32B.vhd
DDS\data.mif
DDS\db\altsyncram_3mi2.tdf
DDS\db\altsyncram_4f51.tdf
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DDS\db\altsyncram_ff51.tdf
DDS\db\altsyncram_mbj2.tdf
DDS\db\cmpr_fnh.tdf
DDS\db\cntr_5af.tdf
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DDS\db\DDS.sld_design_entry.sci
DDS\db\DDS.sld_design_entry_dsc.sci
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DDS\db\decode_ogi.tdf
DDS\db\wed.zsf
DDS\DDS.asm.rpt
DDS\DDS.done
DDS\DDS.fit.rpt
DDS\DDS.fit.smsg
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DDS\DDS.flow.rpt
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DDS\DDS.pin
DDS\DDS.pof
DDS\DDS.qpf
DDS\DDS.qsf
DDS\DDS.qws
DDS\DDS.sim.rpt
DDS\DDS.sof
DDS\DDS.tan.rpt
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DDS\DDS.vhd
DDS\DDS.vwf
DDS\LCD.vhd
DDS\REG10B.vhd
DDS\REG32B.vhd
DDS\SIN_ROM.cmp
DDS\SIN_ROM.vhd
DDS\sin_rom_10.mif
DDS\sopc_builder_debug_log.txt
DDS\stp1.stp
DDS\.sopc_builder
DDS\db
DDS

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