Introduction - If you have any usage issues, please Google them yourself
Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles
Packet : 41695080freq_cnt.rar filelist
freq_cnt\db\freq_cnt.(0).cnf.cdb
freq_cnt\db\freq_cnt.(0).cnf.hdb
freq_cnt\db\freq_cnt.asm.qmsg
freq_cnt\db\freq_cnt.cbx.xml
freq_cnt\db\freq_cnt.cmp.cdb
freq_cnt\db\freq_cnt.cmp.hdb
freq_cnt\db\freq_cnt.cmp.kpt
freq_cnt\db\freq_cnt.cmp.logdb
freq_cnt\db\freq_cnt.cmp.rdb
freq_cnt\db\freq_cnt.cmp.tdb
freq_cnt\db\freq_cnt.cmp0.ddb
freq_cnt\db\freq_cnt.cmp2.ddb
freq_cnt\db\freq_cnt.dbp
freq_cnt\db\freq_cnt.db_info
freq_cnt\db\freq_cnt.eco.cdb
freq_cnt\db\freq_cnt.eds_overflow
freq_cnt\db\freq_cnt.fit.qmsg
freq_cnt\db\freq_cnt.hier_info
freq_cnt\db\freq_cnt.hif
freq_cnt\db\freq_cnt.map.cdb
freq_cnt\db\freq_cnt.map.hdb
freq_cnt\db\freq_cnt.map.logdb
freq_cnt\db\freq_cnt.map.qmsg
freq_cnt\db\freq_cnt.pre_map.cdb
freq_cnt\db\freq_cnt.pre_map.hdb
freq_cnt\db\freq_cnt.psp
freq_cnt\db\freq_cnt.rtlv.hdb
freq_cnt\db\freq_cnt.rtlv_sg.cdb
freq_cnt\db\freq_cnt.rtlv_sg_swap.cdb
freq_cnt\db\freq_cnt.sgdiff.cdb
freq_cnt\db\freq_cnt.sgdiff.hdb
freq_cnt\db\freq_cnt.signalprobe.cdb
freq_cnt\db\freq_cnt.sim.hdb
freq_cnt\db\freq_cnt.sim.qmsg
freq_cnt\db\freq_cnt.sim.rdb
freq_cnt\db\freq_cnt.sim.vwf
freq_cnt\db\freq_cnt.sim_ori.vwf
freq_cnt\db\freq_cnt.sld_design_entry.sci
freq_cnt\db\freq_cnt.sld_design_entry_dsc.sci
freq_cnt\db\freq_cnt.syn_hier_info
freq_cnt\db\freq_cnt.tan.qmsg
freq_cnt\db\wed.zsf
freq_cnt\db
freq_cnt\freq_cnt.asm.rpt
freq_cnt\freq_cnt.done
freq_cnt\freq_cnt.fit.rpt
freq_cnt\freq_cnt.fit.smsg
freq_cnt\freq_cnt.fit.summary
freq_cnt\freq_cnt.flow.rpt
freq_cnt\freq_cnt.map.rpt
freq_cnt\freq_cnt.map.summary
freq_cnt\freq_cnt.pin
freq_cnt\freq_cnt.qpf
freq_cnt\freq_cnt.qsf
freq_cnt\freq_cnt.qws
freq_cnt\freq_cnt.sim.rpt
freq_cnt\freq_cnt.tan.rpt
freq_cnt\freq_cnt.tan.summary
freq_cnt\freq_cnt.vhd
freq_cnt\freq_cnt.vwf
freq_cnt