Using FPGA to achieve the VGA interface program, the language used is VHDL hardware description language, we can see under the light of the devices used are Altera EP2c35

Packet : 21840287s8_vga.rar filelist
S8_VGA
S8_VGA\Doc
S8_VGA\Doc\程序说明.txt
S8_VGA\Proj
S8_VGA\Proj\cmp_state.ini
S8_VGA\Proj\ColorBar.asm.rpt
S8_VGA\Proj\ColorBar.cdf
S8_VGA\Proj\ColorBar.done
S8_VGA\Proj\ColorBar.eda.rpt
S8_VGA\Proj\ColorBar.fit.eqn
S8_VGA\Proj\ColorBar.fit.rpt
S8_VGA\Proj\ColorBar.fit.summary
S8_VGA\Proj\ColorBar.flow.rpt
S8_VGA\Proj\ColorBar.map.eqn
S8_VGA\Proj\ColorBar.map.rpt
S8_VGA\Proj\ColorBar.map.summary
S8_VGA\Proj\ColorBar.pin
S8_VGA\Proj\ColorBar.pof
S8_VGA\Proj\ColorBar.qpf
S8_VGA\Proj\ColorBar.qsf
S8_VGA\Proj\ColorBar.qws
S8_VGA\Proj\ColorBar.sof
S8_VGA\Proj\ColorBar.tan.rpt
S8_VGA\Proj\ColorBar.tan.summary
S8_VGA\Proj\ColorBar_assignment_defaults.qdf
S8_VGA\Proj\stp1.stp
S8_VGA\Proj\VGA_PLL.bsf
S8_VGA\Proj\VGA_PLL.v
S8_VGA\Proj\vga_vl.bsf
S8_VGA\Proj\db
S8_VGA\Proj\db\altsyncram_1f92.tdf
S8_VGA\Proj\db\altsyncram_fl82.tdf
S8_VGA\Proj\db\altsyncram_hl82.tdf
S8_VGA\Proj\db\altsyncram_jm92.tdf
S8_VGA\Proj\db\altsyncram_pd91.tdf
S8_VGA\Proj\db\cntr_1a9.tdf
S8_VGA\Proj\db\cntr_7v7.tdf
S8_VGA\Proj\db\cntr_909.tdf
S8_VGA\Proj\db\cntr_d58.tdf
S8_VGA\Proj\db\cntr_f29.tdf
S8_VGA\Proj\db\cntr_gq7.tdf
S8_VGA\Proj\db\cntr_h5a.tdf
S8_VGA\Proj\db\cntr_ln7.tdf
S8_VGA\Proj\db\cntr_no8.tdf
S8_VGA\Proj\db\cntr_qt7.tdf
S8_VGA\Proj\db\cntr_rt7.tdf
S8_VGA\Proj\db\cntr_vt9.tdf
S8_VGA\Proj\db\ColorBar.(3).cnf.cdb
S8_VGA\Proj\db\ColorBar.(3).cnf.hdb
S8_VGA\Proj\db\ColorBar.rtlv_sg_swap.cdb
S8_VGA\Proj\db\ColorBar.pre_map.cdb
S8_VGA\Proj\db\ColorBar.fit.qmsg
S8_VGA\Proj\db\ColorBar.cmp.logdb
S8_VGA\Proj\db\ColorBar.(0).cnf.cdb
S8_VGA\Proj\db\ColorBar.pre_map.hdb
S8_VGA\Proj\db\ColorBar.map.cdb
S8_VGA\Proj\db\ColorBar.(1).cnf.cdb
S8_VGA\Proj\db\ColorBar.asm.qmsg
S8_VGA\Proj\db\ColorBar.(1).cnf.hdb
S8_VGA\Proj\db\ColorBar.tan.qmsg
S8_VGA\Proj\db\ColorBar.eda.qmsg
S8_VGA\Proj\db\ColorBar.rtlv.hdb
S8_VGA\Proj\db\ColorBar.sld_design_entry_dsc.sci
S8_VGA\Proj\db\ColorBar.(0).cnf.hdb
S8_VGA\Proj\db\ColorBar.sgdiff.hdb
S8_VGA\Proj\db\ColorBar.(17).cnf.cdb
S8_VGA\Proj\db\ColorBar.rtlv_sg.cdb
S8_VGA\Proj\db\ColorBar.map.logdb
S8_VGA\Proj\db\ColorBar.cmp.cdb
S8_VGA\Proj\db\ColorBar.(17).cnf.hdb
S8_VGA\Proj\db\ColorBar.(20).cnf.cdb
S8_VGA\Proj\db\ColorBar.(20).cnf.hdb
S8_VGA\Proj\db\ColorBar.(34).cnf.cdb
S8_VGA\Proj\db\ColorBar.sgdiff.cdb
S8_VGA\Proj\db\ColorBar.eco.cdb
S8_VGA\Proj\db\ColorBar.map.hdb
S8_VGA\Proj\db\ColorBar.map.qmsg
S8_VGA\Proj\db\ColorBar.sld_design_entry.sci
S8_VGA\Proj\db\ColorBar.cmp2.ddb
S8_VGA\Proj\db\ColorBar.signalprobe.cdb
S8_VGA\Proj\db\ColorBar.cmp.tdb
S8_VGA\Proj\db\ColorBar.cmp.rdb
S8_VGA\Proj\db\ColorBar.asm_labs.ddb
S8_VGA\Proj\db\ColorBar.cmp.hdb
S8_VGA\Proj\db\ColorBar.cmp0.ddb
S8_VGA\Proj\db\ColorBar.(34).cnf.hdb
S8_VGA\Proj\db\ColorBar.(37).cnf.cdb
S8_VGA\Proj\db\ColorBar.(37).cnf.hdb
S8_VGA\Proj\db\ColorBar.(43).cnf.cdb
S8_VGA\Proj\db\ColorBar.(43).cnf.hdb
S8_VGA\Proj\db\ColorBar.(51).cnf.cdb
S8_VGA\Proj\db\ColorBar.(51).cnf.hdb
S8_VGA\Proj\db\ColorBar.(56).cnf.cdb
S8_VGA\Proj\db\ColorBar.(56).cnf.hdb
S8_VGA\Proj\db\ColorBar.cbx.xml
S8_VGA\Proj\db\ColorBar.db_info
S8_VGA\Proj\db\ColorBar.hier_info
S8_VGA\Proj\db\ColorBar.hif
S8_VGA\Proj\db\ColorBar.psp
S8_VGA\Proj\db\ColorBar.syn_hier_info
S8_VGA\Proj\db\ColorBar_cmp.qrpt
S8_VGA\Proj\db\decode_9ie.tdf
S8_VGA\Proj\db\decode_rpe.tdf
S8_VGA\Proj\db\ColorBar.(2).cnf.cdb
S8_VGA\Proj\db\ColorBar.(2).cnf.hdb
S8_VGA\Proj\simulation
S8_VGA\Proj\simulation\modelsim
S8_VGA\Proj\simulation\modelsim\ColorBar.vo
S8_VGA\Proj\simulation\modelsim\ColorBar_modelsim.xrf
S8_VGA\Proj\simulation\modelsim\ColorBar_v.sdo
S8_VGA\Src
S8_VGA\Src\ColorBar.bdf
S8_VGA\Src\ColorBar.bsf
S8_VGA\Src\vga_vl.v

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