small verilogHDL entry procedures, the main function of the completion of decoding, from a 4 to 2 hexadecimal number into an 8-bit BCD you

Packet : 71477189bcd2.rar filelist
BCD2\BCD2.asm.rpt
BCD2\BCD2.cdf
BCD2\BCD2.done
BCD2\BCD2.fit.eqn
BCD2\BCD2.fit.rpt
BCD2\BCD2.fit.summary
BCD2\BCD2.flow.rpt
BCD2\BCD2.map.eqn
BCD2\BCD2.map.rpt
BCD2\BCD2.map.summary
BCD2\BCD2.pin
BCD2\BCD2.pof
BCD2\BCD2.qpf
BCD2\BCD2.qsf
BCD2\BCD2.qws
BCD2\BCD2.sim.rpt
BCD2\BCD2.sof
BCD2\BCD2.tan.rpt
BCD2\BCD2.tan.summary
BCD2\BCD2.v
BCD2\BCD2.vwf
BCD2\cmp_state.ini
BCD2\db\add_sub_4rh.tdf
BCD2\db\BCD2.(0).cnf.cdb
BCD2\db\BCD2.(0).cnf.hdb
BCD2\db\BCD2.asm.qmsg
BCD2\db\BCD2.cbx.xml
BCD2\db\BCD2.cmp.cdb
BCD2\db\BCD2.cmp.hdb
BCD2\db\BCD2.cmp.rdb
BCD2\db\BCD2.cmp.tdb
BCD2\db\BCD2.cmp0.ddb
BCD2\db\BCD2.db_info
BCD2\db\BCD2.eco.cdb
BCD2\db\BCD2.eds_overflow
BCD2\db\BCD2.fit.qmsg
BCD2\db\BCD2.fnsim.hdb
BCD2\db\BCD2.hier_info
BCD2\db\BCD2.hif
BCD2\db\BCD2.map.cdb
BCD2\db\BCD2.map.hdb
BCD2\db\BCD2.map.qmsg
BCD2\db\BCD2.pre_map.cdb
BCD2\db\BCD2.pre_map.hdb
BCD2\db\BCD2.psp
BCD2\db\BCD2.rtlv.hdb
BCD2\db\BCD2.rtlv_sg.cdb
BCD2\db\BCD2.rtlv_sg_swap.cdb
BCD2\db\BCD2.sgdiff.cdb
BCD2\db\BCD2.sgdiff.hdb
BCD2\db\BCD2.signalprobe.cdb
BCD2\db\BCD2.sim.hdb
BCD2\db\BCD2.sim.qmsg
BCD2\db\BCD2.sim.rdb
BCD2\db\BCD2.sld_design_entry.sci
BCD2\db\BCD2.sld_design_entry_dsc.sci
BCD2\db\BCD2.syn_hier_info
BCD2\db\BCD2.tan.qmsg
BCD2\db\BCD2_cmp.qrpt
BCD2\db
BCD2

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