Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD

Packet : 5956464usb.rar filelist
usb\驱动\EZUSBW2K.INF
usb\驱动\EZMON.SYS
usb\驱动\EZUSB.SYS
usb\驱动
usb\PC端程序\send1\send.clw
usb\PC端程序\send1\ReadMe.txt
usb\PC端程序\send1\send.h
usb\PC端程序\send1\send.cpp
usb\PC端程序\send1\StdAfx.h
usb\PC端程序\send1\StdAfx.cpp
usb\PC端程序\send1\send.dsp
usb\PC端程序\send1\send.dsw
usb\PC端程序\send1\send.plg
usb\PC端程序\send1\send.ncb
usb\PC端程序\send1\Resource.h
usb\PC端程序\send1\ezusbsys.h
usb\PC端程序\send1\sendDlg.h
usb\PC端程序\send1\sendDlg.cpp
usb\PC端程序\send1\send.rc
usb\PC端程序\send1\send.aps
usb\PC端程序\send1\send.opt
usb\PC端程序\send1\res\send.rc2
usb\PC端程序\send1\res\send.ico
usb\PC端程序\send1\res
usb\PC端程序\send1\Debug
usb\PC端程序\send1
usb\PC端程序\receive\receive.opt
usb\PC端程序\receive\receiveDlg.cpp
usb\PC端程序\receive\receive.clw
usb\PC端程序\receive\ReadMe.txt
usb\PC端程序\receive\receive.h
usb\PC端程序\receive\receive.cpp
usb\PC端程序\receive\StdAfx.h
usb\PC端程序\receive\StdAfx.cpp
usb\PC端程序\receive\receive.dsp
usb\PC端程序\receive\receive.ncb
usb\PC端程序\receive\ezusbsys.h
usb\PC端程序\receive\receive.plg
usb\PC端程序\receive\Resource.h
usb\PC端程序\receive\receiveDlg.h
usb\PC端程序\receive\receive.dsw
usb\PC端程序\receive\receive.rc
usb\PC端程序\receive\receive.aps
usb\PC端程序\receive\Debug
usb\PC端程序\receive\res\receive.rc2
usb\PC端程序\receive\res\receive.ico
usb\PC端程序\receive\res
usb\PC端程序\receive
usb\PC端程序
usb\USB固件程序\FX2 Slave FIFO\build.bat
usb\USB固件程序\FX2 Slave FIFO\dscr.a51
usb\USB固件程序\FX2 Slave FIFO\fw.c
usb\USB固件程序\FX2 Slave FIFO\FX2 xFIFO 8-bit Async Build ENV.pif
usb\USB固件程序\FX2 Slave FIFO\readme.txt
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.c
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.hex
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.iic
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.lnp
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.plg
usb\USB固件程序\FX2 Slave FIFO\USBJmpTb.OBJ
usb\USB固件程序\FX2 Slave FIFO\Ezusb.lib
usb\USB固件程序\FX2 Slave FIFO\DSCR.LST
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.M51
usb\USB固件程序\FX2 Slave FIFO\tcxmaster_Uv2.Bak
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.Uv2
usb\USB固件程序\FX2 Slave FIFO\FW.LST
usb\USB固件程序\FX2 Slave FIFO\FW.OBJ
usb\USB固件程序\FX2 Slave FIFO\DSCR.OBJ
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.LST
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.OBJ
usb\USB固件程序\FX2 Slave FIFO\tcxmaster
usb\USB固件程序\FX2 Slave FIFO\tcxmaster_Opt.Bak
usb\USB固件程序\FX2 Slave FIFO\tcxmaster.Opt
usb\USB固件程序\FX2 Slave FIFO
usb\USB固件程序
usb\FPGA_CPLD\USB_TEST\USB_TEST.ise_ISE_Backup
usb\FPGA_CPLD\USB_TEST\usbtest.vhd
usb\FPGA_CPLD\USB_TEST\usbtest.prj
usb\FPGA_CPLD\USB_TEST\usbtest.xst
usb\FPGA_CPLD\USB_TEST\usbtest.cmd_log
usb\FPGA_CPLD\USB_TEST\usbtest.syr
usb\FPGA_CPLD\USB_TEST\usbtest.lso
usb\FPGA_CPLD\USB_TEST\usbtest.stx
usb\FPGA_CPLD\USB_TEST\usbtest.ngr
usb\FPGA_CPLD\USB_TEST\usbtest.ngc
usb\FPGA_CPLD\USB_TEST\usbtest.ucf
usb\FPGA_CPLD\USB_TEST\usbtest.lfp
usb\FPGA_CPLD\USB_TEST\pepExtractor.prj
usb\FPGA_CPLD\USB_TEST\_pace.ucf
usb\FPGA_CPLD\USB_TEST\usbtest.bld
usb\FPGA_CPLD\USB_TEST\usbtest.ngd
usb\FPGA_CPLD\USB_TEST\usbtest.rpt
usb\FPGA_CPLD\USB_TEST\usbtest.xml
usb\FPGA_CPLD\USB_TEST\usbtest_build.xml
usb\FPGA_CPLD\USB_TEST\usbtest.pad
usb\FPGA_CPLD\USB_TEST\usbtest_pad.csv
usb\FPGA_CPLD\USB_TEST\usbtest.vm6
usb\FPGA_CPLD\USB_TEST\usbtest.mfd
usb\FPGA_CPLD\USB_TEST\tmperr.err
usb\FPGA_CPLD\USB_TEST\usbtest.gyd
usb\FPGA_CPLD\USB_TEST\usbtest.nga
usb\FPGA_CPLD\USB_TEST\usbtest.tspec
usb\FPGA_CPLD\USB_TEST\usbtest.tim
usb\FPGA_CPLD\USB_TEST\usbtest.jed
usb\FPGA_CPLD\USB_TEST\usbtest.pnx
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\acr2_logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\blackBar.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\cpldBanner.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\cr2s_logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\fitterRpt.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\spacer.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\timingRpt.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\xa9500xl_logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images\xbr_logo.jpg
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usb\FPGA_CPLD\USB_TEST\usbtest_html\images\xc9500xv_logo.jpg
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usb\FPGA_CPLD\USB_TEST\usbtest_html\images\logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\images
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usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\genreport.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\leftnav.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\report.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\timing_report.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\topnav.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\cpldta_style.css
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim\toc.css
usb\FPGA_CPLD\USB_TEST\usbtest_html\tim
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pins.js
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\report.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pin_legXbr.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pinsdoc.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pinview.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\tooltips.js
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pin_legXpla3.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\summary.js
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\topnav.js
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\plugin.js
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\prev.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pindiagram.gif
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\print.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\result.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\style.css
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\products.gif
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\purchase.gif
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\search.gif
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\xc9500xl_logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\spacer.gif
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\summarydoc.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\support.gif
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\unmaplogicdoc.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\topnav.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\leftnav.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\ascii.tmp
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\eqns.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\summary.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\options.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\errs.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\failtable.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\logicleft.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\inputleft.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\pins.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\wait.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\maplogic_00.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\maplogic_02.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\mapinput_00.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\mapinput_02.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB2.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB3.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB4.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB5.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB6.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\fbs_FB8.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\appletref.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\asciidoc.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\checkNS4.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\coolrunnerII_logo.jpg
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\coolrunner_logo.jpg
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\logic_legXbr.htm
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\optionsdoc.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\paths.js
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usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\ascii.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit\applet.htm
usb\FPGA_CPLD\USB_TEST\usbtest_html\fit
usb\FPGA_CPLD\USB_TEST\usbtest_html
usb\FPGA_CPLD\USB_TEST\_ngo\netlist.lst
usb\FPGA_CPLD\USB_TEST\_ngo
usb\FPGA_CPLD\USB_TEST\xst\dump.xst\usbtest.prj\ngx\notopt
usb\FPGA_CPLD\USB_TEST\xst\dump.xst\usbtest.prj\ngx\opt
usb\FPGA_CPLD\USB_TEST\xst\dump.xst\usbtest.prj\ngx
usb\FPGA_CPLD\USB_TEST\xst\dump.xst\usbtest.prj
usb\FPGA_CPLD\USB_TEST\xst\dump.xst
usb\FPGA_CPLD\USB_TEST\xst\work\hdllib.ref
usb\FPGA_CPLD\USB_TEST\xst\work\sub00\vhpl00.vho
usb\FPGA_CPLD\USB_TEST\xst\work\sub00\vhpl01.vho
usb\FPGA_CPLD\USB_TEST\xst\work\sub00
usb\FPGA_CPLD\USB_TEST\xst\work\hdpdeps.ref
usb\FPGA_CPLD\USB_TEST\xst\work
usb\FPGA_CPLD\USB_TEST\xst\projnav.tmp
usb\FPGA_CPLD\USB_TEST\xst
usb\FPGA_CPLD\USB_TEST\_xmsgs\xst.xmsgs
usb\FPGA_CPLD\USB_TEST\_xmsgs\ngdbuild.xmsgs
usb\FPGA_CPLD\USB_TEST\_xmsgs\cpldfit.xmsgs
usb\FPGA_CPLD\USB_TEST\_xmsgs
usb\FPGA_CPLD\USB_TEST\USB_TEST.ise
usb\FPGA_CPLD\USB_TEST
usb\FPGA_CPLD
usb

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