random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the

Packet : 25811251rng.rar filelist
verilog\CVS\Entries
verilog\CVS\Entries.Extra
verilog\CVS\Entries.Extra.Old
verilog\CVS\Entries.Old
verilog\CVS\Repository
verilog\CVS\Root
verilog\CVS\Template
verilog\rng.v
verilog\CVS
verilog
verilog\Tkacik.pdf

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