Introduction - If you have any usage issues, please Google them yourself
Using VHDL realization of 2,4,8 sub-frequency design, by the compiler, waveform simulation success
Packet : 7941923div248.rar filelist
div248\db\div248.db_info
div248\db\div248.eco.cdb
div248\db\div248.sim_ori.vwf
div248\db\div248.sld_design_entry.sci
div248\db\wed.zsf
div248\db
div248\div248.asm.rpt
div248\div248.bsf
div248\div248.done
div248\div248.fit.rpt
div248\div248.fit.smsg
div248\div248.fit.summary
div248\div248.flow.rpt
div248\div248.map.rpt
div248\div248.map.summary
div248\div248.pin
div248\div248.pof
div248\div248.qpf
div248\div248.qsf
div248\div248.qws
div248\div248.sim.rpt
div248\div248.sof
div248\div248.tan.rpt
div248\div248.tan.summary
div248\div248.vhd
div248\div248.vwf
div248\div248_assignment_defaults.qdf
div248