Introduction - If you have any usage issues, please Google them yourself
This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Packet : 79419143v2_fifo_vhd_258.zip filelist
v2_fifo_vhd_258/fifoctlr_cc_tb.vhd
v2_fifo_vhd_258/fifoctlr_cc_v2.vhd
v2_fifo_vhd_258/fifoctlr_ic_tb.vhd
v2_fifo_vhd_258/fifoctlr_ic_v2.vhd
v2_fifo_vhd_258/fifofaq.txt
v2_fifo_vhd_258/readme
v2_fifo_vhd_258/v2_fifo_vhd_258.ise