Packet : 25811262oc8051.rar filelist
OC8051\.nclaunch.dd
OC8051\asm\cast.c
OC8051\asm\counter_test.asm
OC8051\asm\DIV16U.asm
OC8051\asm\divmul.c
OC8051\asm\fib.c
OC8051\asm\gcd.c
OC8051\asm\hex\cast.hex
OC8051\asm\hex
OC8051\asm\int2bin.c
OC8051\asm\interrupt_test.asm
OC8051\asm\lcall.asm
OC8051\asm\negcnt.c
OC8051\asm\r_bank.asm
OC8051\asm\serial.asm
OC8051\asm\serial_test.asm
OC8051\asm\sort.c
OC8051\asm\sqroot.c
OC8051\asm\test.asm
OC8051\asm\testall.asm
OC8051\asm\testall.c
OC8051\asm\timer.asm
OC8051\asm\timer2_test.asm
OC8051\asm\timer_test.asm
OC8051\asm\v\cast.v
OC8051\asm\v\counter_test.v
OC8051\asm\v\counter_test.v.bak
OC8051\asm\v\div16u.v
OC8051\asm\v\divmul.v
OC8051\asm\v\fib.v
OC8051\asm\v\gcd.v
OC8051\asm\v\int2bin.v
OC8051\asm\v\interrupt_test.v
OC8051\asm\v\lcall.v
OC8051\asm\v\negcnt.v
OC8051\asm\v\r_bank.v
OC8051\asm\v\serial_test.v
OC8051\asm\v\sort.v
OC8051\asm\v\sqroot.v
OC8051\asm\v\testall.v
OC8051\asm\v\timer_test.v
OC8051\asm\v\xram.v
OC8051\asm\v\xram_m.v
OC8051\asm\v
OC8051\asm\xram.c
OC8051\asm\xram_m.c
OC8051\asm\xrom_test.asm
OC8051\asm
OC8051\bench\verilog\oc8051_fpga_tb.v
OC8051\bench\verilog\oc8051_serial.v
OC8051\bench\verilog\oc8051_tb.v
OC8051\bench\verilog\oc8051_timescale.v
OC8051\bench\verilog\oc8051_uart_test.v
OC8051\bench\verilog\oc8051_xram.v
OC8051\bench\verilog\oc8051_xrom.v
OC8051\bench\verilog
OC8051\bench
OC8051\doc\pdf\oc8051_spec.pdf
OC8051\doc\pdf
OC8051\doc\scr\oc8051_design.doc
OC8051\doc\scr
OC8051\doc
OC8051\interface.jpg
OC8051\overview.txt
OC8051\rtl\verilog\attic\oc8051_alu_src1_sel.v
OC8051\rtl\verilog\attic\oc8051_alu_src2_sel.v
OC8051\rtl\verilog\attic\oc8051_alu_src3_sel.v
OC8051\rtl\verilog\attic\oc8051_ext_addr_sel.v
OC8051\rtl\verilog\attic\oc8051_fpga_top.v
OC8051\rtl\verilog\attic\oc8051_immediate_sel.v
OC8051\rtl\verilog\attic\oc8051_op_select.v
OC8051\rtl\verilog\attic\oc8051_pc.v
OC8051\rtl\verilog\attic\oc8051_ram.v
OC8051\rtl\verilog\attic\oc8051_ram_adr_sel.v
OC8051\rtl\verilog\attic\oc8051_ram_rd_sel.v
OC8051\rtl\verilog\attic\oc8051_ram_sel.v
OC8051\rtl\verilog\attic\oc8051_ram_wr_sel.v
OC8051\rtl\verilog\attic\oc8051_reg1.v
OC8051\rtl\verilog\attic\oc8051_reg2.v
OC8051\rtl\verilog\attic\oc8051_reg3.v
OC8051\rtl\verilog\attic\oc8051_reg4.v
OC8051\rtl\verilog\attic\oc8051_reg8.v
OC8051\rtl\verilog\attic\oc8051_rom_addr_sel.v
OC8051\rtl\verilog\attic\oc8051_tb.v
OC8051\rtl\verilog\attic
OC8051\rtl\verilog\oc8051_acc.v
OC8051\rtl\verilog\oc8051_alu.v
OC8051\rtl\verilog\oc8051_alu_src_sel.v
OC8051\rtl\verilog\oc8051_alu_test.v
OC8051\rtl\verilog\oc8051_b_register.v
OC8051\rtl\verilog\oc8051_cache_ram.v
OC8051\rtl\verilog\oc8051_comp.v
OC8051\rtl\verilog\oc8051_cy_select.v
OC8051\rtl\verilog\oc8051_decoder.v
OC8051\rtl\verilog\oc8051_defines.v
OC8051\rtl\verilog\oc8051_divide.v
OC8051\rtl\verilog\oc8051_dptr.v
OC8051\rtl\verilog\oc8051_icache.v
OC8051\rtl\verilog\oc8051_indi_addr.v
OC8051\rtl\verilog\oc8051_int.v
OC8051\rtl\verilog\oc8051_memory_interface.v
OC8051\rtl\verilog\oc8051_multiply.v
OC8051\rtl\verilog\oc8051_ports.v
OC8051\rtl\verilog\oc8051_psw.v
OC8051\rtl\verilog\oc8051_ram_256x8_two_bist.v
OC8051\rtl\verilog\oc8051_ram_64x32_dual_bist.v
OC8051\rtl\verilog\oc8051_ram_top.v
OC8051\rtl\verilog\oc8051_rom.v
OC8051\rtl\verilog\oc8051_sfr.v
OC8051\rtl\verilog\oc8051_sp.v
OC8051\rtl\verilog\oc8051_tc.v
OC8051\rtl\verilog\oc8051_tc2.v
OC8051\rtl\verilog\oc8051_timescale.v
OC8051\rtl\verilog\oc8051_top.v
OC8051\rtl\verilog\oc8051_uart.v
OC8051\rtl\verilog\oc8051_wb_iinterface.v
OC8051\rtl\verilog\read.me
OC8051\rtl\verilog\ue_chinese.gip
OC8051\rtl\verilog
OC8051\rtl
OC8051\sim\rtl_sim\bin\INCA_libs\cds.lib
OC8051\sim\rtl_sim\bin\INCA_libs\hdl.var
OC8051\sim\rtl_sim\bin\INCA_libs\worklib\inca.linux.138.pak
OC8051\sim\rtl_sim\bin\INCA_libs\worklib
OC8051\sim\rtl_sim\bin\INCA_libs
OC8051\sim\rtl_sim\bin
OC8051\sim\rtl_sim\log\ncelab.log
OC8051\sim\rtl_sim\log\ncsim.log
OC8051\sim\rtl_sim\log\ncvlog.log
OC8051\sim\rtl_sim\log
OC8051\sim\rtl_sim\oc8051_ea.in
OC8051\sim\rtl_sim\oc8051_eai.in
OC8051\sim\rtl_sim\oc8051_eax.in
OC8051\sim\rtl_sim\out\cast.out
OC8051\sim\rtl_sim\out\counter_test.out
OC8051\sim\rtl_sim\out\div16u.out
OC8051\sim\rtl_sim\out\divmul.out
OC8051\sim\rtl_sim\out\fib.out
OC8051\sim\rtl_sim\out\gcd.out
OC8051\sim\rtl_sim\out\int2bin.out
OC8051\sim\rtl_sim\out\interrupt_test.out
OC8051\sim\rtl_sim\out\lcall.out
OC8051\sim\rtl_sim\out\ncelab.out
OC8051\sim\rtl_sim\out\ncprep.out
OC8051\sim\rtl_sim\out\ncvlog.out
OC8051\sim\rtl_sim\out\negcnt.out
OC8051\sim\rtl_sim\out\r_bank.out
OC8051\sim\rtl_sim\out\serial_test.out
OC8051\sim\rtl_sim\out\sort.out
OC8051\sim\rtl_sim\out\sqroot.out
OC8051\sim\rtl_sim\out\testall.out
OC8051\sim\rtl_sim\out\timer.out
OC8051\sim\rtl_sim\out\timer_test.out
OC8051\sim\rtl_sim\out\xram_m.out
OC8051\sim\rtl_sim\out\xrom_m.out
OC8051\sim\rtl_sim\out
OC8051\sim\rtl_sim\run\internal.do
OC8051\sim\rtl_sim\run\make.8;content-type=text%2Fplain
OC8051\sim\rtl_sim\run\make_fpga.1;content-type=text%2Fplain
OC8051\sim\rtl_sim\run\make_verilog.7;content-type=text%2Fplain
OC8051\sim\rtl_sim\run\oc8051_defines.v
OC8051\sim\rtl_sim\run\oc8051_timescale.v
OC8051\sim\rtl_sim\run\run.9;content-type=text%2Fplain
OC8051\sim\rtl_sim\run\run_sim.scr
OC8051\sim\rtl_sim\run\verilog.log
OC8051\sim\rtl_sim\run
OC8051\sim\rtl_sim\src\Attic\cast.in
OC8051\sim\rtl_sim\src\Attic\cast.vec
OC8051\sim\rtl_sim\src\Attic\counter_test.in
OC8051\sim\rtl_sim\src\Attic\counter_test.vec
OC8051\sim\rtl_sim\src\Attic\div16u.in
OC8051\sim\rtl_sim\src\Attic\div16u.vec
OC8051\sim\rtl_sim\src\Attic\divmul.in
OC8051\sim\rtl_sim\src\Attic\divmul.vec
OC8051\sim\rtl_sim\src\Attic\fib.in
OC8051\sim\rtl_sim\src\Attic\fib.vec
OC8051\sim\rtl_sim\src\Attic\gcd.in
OC8051\sim\rtl_sim\src\Attic\gcd.vec
OC8051\sim\rtl_sim\src\Attic\int2bin.in
OC8051\sim\rtl_sim\src\Attic\int2bin.vec
OC8051\sim\rtl_sim\src\Attic\interrupt_test.asm
OC8051\sim\rtl_sim\src\Attic\interrupt_test.in
OC8051\sim\rtl_sim\src\Attic\interrupt_test.vec
OC8051\sim\rtl_sim\src\Attic\lcall.in
OC8051\sim\rtl_sim\src\Attic\lcall.vec
OC8051\sim\rtl_sim\src\Attic\negcnt.in
OC8051\sim\rtl_sim\src\Attic\negcnt.vec
OC8051\sim\rtl_sim\src\Attic\oc8051_rom.in
OC8051\sim\rtl_sim\src\Attic\oc8051_test.vec
OC8051\sim\rtl_sim\src\Attic\r_bank.in
OC8051\sim\rtl_sim\src\Attic\r_bank.vec
OC8051\sim\rtl_sim\src\Attic\serial.vec
OC8051\sim\rtl_sim\src\Attic\serial_test.in
OC8051\sim\rtl_sim\src\Attic\serial_test.vec
OC8051\sim\rtl_sim\src\Attic\sort.in
OC8051\sim\rtl_sim\src\Attic\sort.vec
OC8051\sim\rtl_sim\src\Attic\sqroot.in
OC8051\sim\rtl_sim\src\Attic\sqroot.vec
OC8051\sim\rtl_sim\src\Attic\testall.in
OC8051\sim\rtl_sim\src\Attic\testall.vec
OC8051\sim\rtl_sim\src\Attic\timer_test.in
OC8051\sim\rtl_sim\src\Attic\timer_test.vec
OC8051\sim\rtl_sim\src\Attic\xram_m.in
OC8051\sim\rtl_sim\src\Attic\xram_m.vec
OC8051\sim\rtl_sim\src\Attic
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_cache_ram.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_ram.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_rom.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_rom_fpga.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_timescale.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_uart_test.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_xram.v
OC8051\sim\rtl_sim\src\verilog\Attic\oc8051_xrom.v
OC8051\sim\rtl_sim\src\verilog\Attic
OC8051\sim\rtl_sim\src\verilog
OC8051\sim\rtl_sim\src
OC8051\sim\rtl_sim
OC8051\sim
OC8051\sw\oc8051_Rom_Maker.exe
OC8051\sw\read.me
OC8051\sw\source\p8051Rom.dof
OC8051\sw\source\p8051Rom.dpr
OC8051\sw\source\p8051Rom.res
OC8051\sw\source\uMain.dcu
OC8051\sw\source\uMain.dfm
OC8051\sw\source\uMain.pas
OC8051\sw\source
OC8051\sw
OC8051\syn\scr\verilog\disp.v
OC8051\syn\scr\verilog\oc8051_cache_ram.v
OC8051\syn\scr\verilog\oc8051_fpga_top.v
OC8051\syn\scr\verilog\oc8051_ram.v
OC8051\syn\scr\verilog\oc8051_rom.v
OC8051\syn\scr\verilog\read.me
OC8051\syn\scr\verilog
OC8051\syn\scr
OC8051\syn\synplify\oc8051.prd
OC8051\syn\synplify\oc8051.prj
OC8051\syn\synplify
OC8051\syn
OC8051

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