include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.

Packet : 379112uart_verilog.zip filelist
rcvr.v
rcvr_tf.v
readme.doc
readme.txt
txmit.v
txmit_tf.v
uart.v

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