FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.

Packet : 69491739can协议控制器的verilog实现.rar filelist
can_acf.v
can_bsp.v
can_btl.v
can_crc.v
can_defines.v
can_fifo.v
can_ibo.v
can_register.v
can_register_asyn.v
can_register_asyn_syn.v
can_register_syn.v
can_registers.v

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