using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.

sap1
....\0.mgf
....\1.mgf
....\3.mgf
....\bde.set
....\compile
....\.......\contents.lib~
....\.......\mega.asm
....\.......\mega.bin
....\.......\mega.dag
....\.......\mega.dbg
....\.......\mega.elb
....\.......\mega.itf
....\.......\mega.mod
....\.......\mega.off
....\.......\sap1.epr
....\.......\sap1.erf
....\.......\sap1.opt
....\.......\sources.sth
....\.......\vcp.mod
....\.......\vcp.top
....\.......\wave0.dat
....\.......\wave1.dat
....\.......\wave10.dat
....\.......\wave11.dat
....\.......\wave12.dat
....\.......\wave2.dat
....\.......\wave3.dat
....\.......\wave4.dat
....\.......\wave5.dat
....\.......\wave6.dat
....\.......\wave7.dat
....\.......\wave8.dat
....\.......\wave9.dat
....\compile.cfg
....\elaboration.log
....\log
....\...\compile.log
....\...\console.log
....\...\find.log
....\...\simulation.log
....\projlib.cfg
....\sap1.adf
....\sap1.LIB
....\sap1.wsp
....\src
....\...\prom.v
....\...\SAP_1.v
....\...\TestBench
....\...\.........\SAP_1_TB.v
....\...\.........\SAP_1_TB_runtest.do
....\...\.........\SAP_1_TB_settings.txt
....\...\Waveform Editor 1.awf

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