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viterbi_fpga

  • Category : DSP program
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  • Update : 2012-11-26
  • Size : 49kb
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  • Author :唐***
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Introduction - If you have any usage issues, please Google them yourself
Viterbi Decoder they simply a realization. Cs252 is a result of the project for all research
Packet file list
(Preview for download)
viterbi_fpga
............\cs252
............\.....\bak
............\.....\perl
............\.....\....\altera_compatible.pl
............\.....\....\change.pl
............\.....\....\conf3
............\.....\....\conf4
............\.....\....\conf6
............\.....\....\conf9
............\.....\....\legible.pl
............\.....\....\noise.pl
............\.....\....\NOTES
............\.....\....\viterbi.pl
............\.....\....\viterbi_producer.pl
............\.....\results
............\.....\rtl
............\.....\...\bak
............\.....\...\conf_3_4_2
............\.....\...\..........\acs1_0.v
............\.....\...\..........\acs1_1.v
............\.....\...\..........\acs2_0.v
............\.....\...\..........\acs2_1.v
............\.....\...\..........\backtrack.v
............\.....\...\..........\block.v
............\.....\...\..........\decoder.v
............\.....\...\..........\defs.h
............\.....\...\..........\in_signal.v
............\.....\...\..........\MS_res_ACS1_0.v
............\.....\...\..........\MS_res_ACS1_1.v
............\.....\...\..........\MS_res_ACS2_0.v
............\.....\...\..........\MS_res_ACS2_1.v
............\.....\...\..........\MS_res_stage.v
............\.....\...\..........\res_acs.v
............\.....\...\..........\res_stage.v
............\.....\...\..........\run
............\.....\...\..........\stage.v
............\.....\...\..........\tmp
............\.....\...\..........\top.v
............\.....\...\..........\verilog.log
............\.....\...\conf_3_8_8
............\.....\...\..........\acs1_0.v
............\.....\...\..........\acs1_1.v
............\.....\...\..........\acs2_0.v
............\.....\...\..........\acs2_1.v
............\.....\...\..........\backtrack.v
............\.....\...\..........\block.v
............\.....\...\..........\decoder.v
............\.....\...\..........\defs.h
............\.....\...\..........\in_signal.v
............\.....\...\..........\MS_res_ACS1_0.v
............\.....\...\..........\MS_res_ACS1_1.v
............\.....\...\..........\MS_res_ACS2_0.v
............\.....\...\..........\MS_res_ACS2_1.v
............\.....\...\..........\MS_res_stage.v
............\.....\...\..........\res_acs.v
............\.....\...\..........\res_stage.v
............\.....\...\..........\run
............\.....\...\..........\stage.v
............\.....\...\..........\tmp
............\.....\...\..........\top.v
............\.....\...\conf_4_12_6
............\.....\...\...........\acs1_0.v
............\.....\...\...........\acs1_1.v
............\.....\...\...........\acs2_0.v
............\.....\...\...........\acs2_1.v
............\.....\...\...........\backtrack.v
............\.....\...\...........\block.v
............\.....\...\...........\decoder.v
............\.....\...\...........\defs.h
............\.....\...\...........\in_signal.v
............\.....\...\...........\MS_res_ACS1_0.v
............\.....\...\...........\MS_res_ACS1_1.v
............\.....\...\...........\MS_res_ACS2_0.v
............\.....\...\...........\MS_res_ACS2_1.v
............\.....\...\...........\MS_res_stage.v
............\.....\...\...........\res_acs.v
............\.....\...\...........\res_stage.v
............\.....\...\...........\run
............\.....\...\...........\stage.v
............\.....\...\...........\tmp
............\.....\...\...........\top.v
............\.....\...\...........\verilog.log
............\.....\...\conf_4_20_1
............\.....\...\...........\acs1_0.v
............\.....\...\...........\acs1_1.v
............\.....\...\...........\acs2_0.v
............\.....\...\...........\acs2_1.v
............\.....\...\...........\backtrack.v
............\.....\...\...........\block.v
............\.....\...\...........\decoder.v
............\.....\...\...........\defs.h
............\.....\...\...........\in_signal.v
............\.....\...\...........\MS_res_ACS1_0.v
............\.....\...\...........\MS_res_ACS1_1.v
............\.....\...\...........\MS_res_ACS2_0.v
............\.....\...\...........\MS_res_ACS2_1.v
............\.....\...\...........\MS_res_sta
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