tell graphics Acquisition Verilog code is very simple first grant

sram_verilog
............\conter1.bsf
............\conter1.v

............\conter1_waveforms.html
............\db
............\..\add_sub_nsh.tdf
............\..\altsyncram_tnr.tdf
............\..\cntr_qed.tdf
............\..\sram.analyze_file.qmsg
............\..\sram.cbx.xml
............\..\sram.cmp.qrpt
............\..\sram.cmp.rdb
............\..\sram.dbp
............\..\sram.db_info
............\..\sram.eco.cdb
............\..\sram.eds_overflow
............\..\sram.fnsim.hdb
............\..\sram.fnsim.qmsg
............\..\sram.hier_info
............\..\sram.hif
............\..\sram.map.cdb
............\..\sram.map.hdb
............\..\sram.map.qmsg
............\..\sram.pre_map.cdb
............\..\sram.pre_map.hdb
............\..\sram.psp
............\..\sram.rtlv.hdb
............\..\sram.rtlv_sg.cdb
............\..\sram.rtlv_sg_swap.cdb
............\..\sram.sgdiff.cdb
............\..\sram.sgdiff.hdb
............\..\sram.sim.hdb
............\..\sram.sim.qmsg
............\..\sram.sim.qrpt
............\..\sram.sim.rdb
............\..\sram.sld_design_entry.sci
............\..\sram.sld_design_entry_dsc.sci
............\..\sram.syn_hier_info
............\M65535.vwf
............\M65536.v
............\mybus.bsf
............\mybus.v
............\ROM.bsf
............\rom.mif
............\ROM.v
............\serv_req_info.txt
............\SRAM.bdf
............\sram.done
............\sram.flow.rpt
............\sram.map.eqn
............\sram.map.rpt
............\sram.map.summary
............\sram.qpf
............\sram.qsf
............\sram.qws
............\sram.sim.rpt
............\SRAM.v
............\SRAM.vwf
............\SRAM_RD.bsf
............\SRAM_RD.v
............\SRAM_RD.vwf
............\SRAM_WR.bsf
............\SRAM_WR.v
............\undo_redo.txt

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