a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.

Packet : 99273891full_add.rar filelist
8位全加器\add1.qpf
8位全加器\add1.qsf
8位全加器\add1.map.eqn
8位全加器\add1.map.rpt
8位全加器\add1.flow.rpt
8位全加器\add1.map.summary
8位全加器\add1.fit.eqn
8位全加器\add1.pin
8位全加器\add1.fit.rpt
8位全加器\add1.fit.summary
8位全加器\add1.sof
8位全加器\add1.pof
8位全加器\add1.asm.rpt
8位全加器\add1.tan.summary
8位全加器\add1.tan.rpt
8位全加器\add1.done
8位全加器\add1.bsf
8位全加器\Block1.bdf
8位全加器\add1.cdf
8位全加器\add1.qws
8位全加器\cmp_state.ini
8位全加器\add1.vhd
8位全加器\db\add1.db_info
8位全加器\db\add1.tan.qmsg
8位全加器\db\add1.map.qmsg
8位全加器\db\add1.sld_design_entry.sci
8位全加器\db\add1.eco.cdb
8位全加器\db\add1.cmp.rdb
8位全加器\db\add1.map.hdb
8位全加器\db\add1.(0).cnf.cdb
8位全加器\db\add1.(0).cnf.hdb
8位全加器\db\add1.cbx.xml
8位全加器\db\add1_cmp.qrpt
8位全加器\db\add1.hif
8位全加器\db\add1.rtlv_sg_swap.cdb
8位全加器\db\add1.pre_map.hdb
8位全加器\db\add1.hier_info
8位全加器\db\add1.rtlv.hdb
8位全加器\db\add1.pre_map.cdb
8位全加器\db\add1.rtlv_sg.cdb
8位全加器\db\add1.sgdiff.hdb
8位全加器\db\add1.fit.qmsg
8位全加器\db\add1.asm.qmsg
8位全加器\db\add1.cmp.hdb
8位全加器\db\add1.psp
8位全加器\db\add1.map.cdb
8位全加器\db\add1.cmp.cdb
8位全加器\db\add1.cmp.tdb
8位全加器\db\add1.syn_hier_info
8位全加器\db\add1.sgdiff.cdb
8位全加器\db\add1.sld_design_entry_dsc.sci
8位全加器\db\add1.cmp0.ddb
8位全加器\db
8位全加器

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