Introduction - If you have any usage issues, please Google them yourself
16 high-speed adder using Verilog language has been successful simulation can be run
Packet : 105230305adder16bit.rar filelist
adder_ver完成版\adder0215.v.bak
adder_ver完成版\adder0215.v
adder_ver完成版\addertestbench.v.bak
adder_ver完成版\addertestbench.v
adder_ver完成版