This paper presents several low-latency mixed-timingFIFO (first-in-first-out) interfaces designs that interface systemson a chip working at different speeds. The connected systemscan be either synchronous or asynchronous. The designs are thenadapted to work between systems with very long interconnectdelays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for latency-insensitive protocols) tomixed-timing domains. The new designs can be made arbitrarilyrobust with regard to metastability and interface operating speeds.Initial simulations for both latency and throughput are promising.

interfaces for mixed-timing systems.pdf

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