fpga cpld common module design, including fpga-based all-digital locks to the ring, Based on the semi-fpga cpld integer divider design and useful

FPGA CPLD中常见模块设计
.......................\一种基于移位寄存器的CAM的Verilog HDL实现.doc
.......................\使用PLD内部锁相环解决系统设计难题.doc
.......................\基于CPLD FPGA的半整数分频器的设计.doc
.......................\基于FPGA的全数字锁相环设计.pdf
.......................\基于FPGA的多种形式分频的设计与实现.doc
.......................\基于FPGA的高频时钟的分频和分配设计.doc
.......................\异步FIFO结构及FPGA设计.doc
.......................\智能全数字锁相环的设计.doc
.......................\用CPLD控制曼彻斯特编解码器.doc
.......................\用VHDL语言在CPLD上实现串行通信.doc
.......................\错误检测与纠正电路的设计与实现.doc

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