verilog prepared pic16c5x clock module

clkgen
......\automake.log
......\clkgen.cmd_log
......\clkgen.dhp
......\clkgen.ldo
......\clkgen.lso
......\clkgen.ngc
......\clkgen.ngr
......\clkgen.npl
......\clkgen.prj
......\clkgen.stx
......\clkgen.syr
......\clkgen.v
......\clkgen_vhdl.prj
......\coregen.log
......\coregen.prj
......\DEFAULT.ANT
......\DEFAULT.TFW
......\dff.cmd_log
......\dff.lso
......\dff.prj
......\dff.syr
......\dff_vhdl.prj
......\fsm_clkgen.cmd_log
......\fsm_clkgen.lso
......\fsm_clkgen.prj
......\fsm_clkgen.syr
......\fsm_clkgen_vhdl.prj
......\results.txt
......\transcript
......\vsim.wlf
......\wave.ado
......\WAVE.ANT
......\wave.fdo
......\wave.tbw
......\WAVE.TFW
......\wave.udo
......\work
......\....\@w@a@v@e
......\....\........\verilog.asm
......\....\........\_primary.dat
......\....\........\_primary.vhd
......\....\clkgen
......\....\......\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\glbl
......\....\....\verilog.asm
......\....\....\_primary.dat
......\....\....\_primary.vhd
......\....\wave
......\....\....\verilog.asm
......\....\....\_primary.dat
......\....\....\_primary.vhd
......\....\_info
......\xst
......\...\work
......\...\....\hdllib.ref
......\...\....\vlg60
......\...\....\.....\clkgen.bin
......\__projnav
......\.........\clkgen.gfl
......\.........\clkgen.xst
......\.........\clkgen_flowplus.gfl
......\.........\coregen.rsp
......\.........\dff.xst
......\.........\fsm_clkgen.xst
......\.........\hb_cmds
......\.........\runXst_tcl.rsp
......\__projnav.log

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