Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~

FIFO_Asyn
.........\FIFO_Buffer.v
.........\FIFO_Buffer.v.bak
.........\my_FIFO_Asyn.cr.mti
.........\my_FIFO_Asyn.mpf
.........\Ser_Par_Conv_32.v
.........\t_FIFO_Clock_Domain_Synch.v
.........\t_FIFO_Clock_Domain_Synch.v.bak
.........\vsim.wlf
.........\work
.........\....\@f@i@f@o_@buffer
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@ser_@par_@conv_32
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\t_@f@i@f@o_@clock_@domain_@synch
.........\....\................................\verilog.asm
.........\....\................................\_primary.dat
.........\....\................................\_primary.vhd
.........\....\write_synchronizer
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\_info
.........\write_synchronizer.v
FIFO_Syn
........\FIFO_Buffer.v
........\FIFO_Syn.cr.mti
........\FIFO_Syn.mpf
........\t_FIFO_Buffer.v
........\vsim.wlf
........\work
........\....\@f@i@f@o_@buffer
........\....\................\verilog.asm
........\....\................\_primary.dat
........\....\................\_primary.vhd
........\....\t_@f@i@f@o_@buffer
........\....\..................\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\_info

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