Based on the quartus2 such as a precision frequency meter design, the main language used in verilogHDL

freq2
.....\BZ_block.bsf
.....\BZ_block.v
.....\Calculater.bsf
.....\Calculater.v
.....\db
.....\..\altsyncram_hji2.tdf
.....\..\altsyncram_jji2.tdf
.....\..\cmpr_5mh.tdf
.....\..\cntr_0sh.tdf
.....\..\cntr_3jf.tdf
.....\..\cntr_4ag.tdf
.....\..\cntr_8he.tdf
.....\..\cntr_9he.tdf
.....\..\cntr_f7f.tdf
.....\..\cntr_pdh.tdf
.....\..\decode_ogi.tdf
.....\..\freq2.asm.qmsg
.....\..\freq2.cbx.xml
.....\..\freq2.cmp.cdb
.....\..\freq2.cmp.hdb
.....\..\freq2.cmp.kpt
.....\..\freq2.cmp.logdb
.....\..\freq2.cmp.rdb
.....\..\freq2.cmp.tdb
.....\..\freq2.cmp0.ddb
.....\..\freq2.dbp
.....\..\freq2.db_info
.....\..\freq2.eco.cdb
.....\..\freq2.fit.qmsg
.....\..\freq2.hier_info
.....\..\freq2.hif
.....\..\freq2.map.cdb
.....\..\freq2.map.hdb
.....\..\freq2.map.logdb
.....\..\freq2.map.qmsg
.....\..\freq2.pre_map.cdb
.....\..\freq2.pre_map.hdb
.....\..\freq2.psp
.....\..\freq2.rpp.qmsg
.....\..\freq2.rtlv.hdb
.....\..\freq2.rtlv_sg.cdb
.....\..\freq2.rtlv_sg_swap.cdb
.....\..\freq2.sgate.rvd
.....\..\freq2.sgate_sm.rvd
.....\..\freq2.sgdiff.cdb
.....\..\freq2.sgdiff.hdb
.....\..\freq2.signalprobe.cdb
.....\..\freq2.sld_design_entry.sci
.....\..\freq2.sld_design_entry_dsc.sci
.....\..\freq2.syn_hier_info
.....\..\freq2.tan.qmsg
.....\DC_block.bsf
.....\DC_block.v
.....\DC_Count.v
.....\freq2.asm.rpt
.....\freq2.bdf
.....\freq2.cdf
.....\freq2.done
.....\freq2.dpf
.....\freq2.fit.rpt
.....\freq2.fit.smsg
.....\freq2.fit.summary
.....\freq2.flow.rpt
.....\freq2.map.rpt
.....\freq2.map.smsg
.....\freq2.map.summary
.....\freq2.pin
.....\freq2.pof
.....\freq2.qpf
.....\freq2.qsf
.....\freq2.qws
.....\freq2.sof
.....\freq2.tan.rpt
.....\freq2.tan.summary
.....\M8.bsf
.....\M8.tdf

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