ARM bahavior model. Contains arm code and design guide.

ARM7
....\arm7
....\....\accessories.v
....\....\addr_reg.v
....\....\alu.v
....\....\alu_structural.v
....\....\and10.dmem
....\....\and10.dmemout
....\....\and10.dmemr
....\....\and10.imem
....\....\and10.regout
....\....\and10.regsr
....\....\arm7.dmem
....\....\arm7.dmemout
....\....\arm7.dmemr
....\....\arm7.imem
....\....\arm7.regout
....\....\arm7.regsr
....\....\arm7.v
....\....\arm7_sys.v
....\....\armcontroller.v
....\....\armdatapath.v
....\....\AVLMemory.v
....\....\barrel.v
....\....\booth.v
....\....\clock.v
....\....\CPUside.v
....\....\defines.v
....\....\do_verilog
....\....\exception.mem
....\....\MemoryInterface.v
....\....\Memoryside.v
....\....\regfile.v
....\....\shift_maker.v
....\....\sign_extend.v
....\....\SimpleMemory.v
....\....\SuperCPSR.v
....\....\testbench_addr_reg.v
....\....\testbench_alu.v
....\....\testbench_arm7.v
....\....\testbench_AVLMemory.v
....\....\testbench_barrel.v
....\....\testbench_booth.v
....\....\testbench_controller.v
....\....\testbench_CPUside.v
....\....\testbench_dedsec.v
....\....\testbench_memory.v
....\....\testbench_regfile.v
....\....\testbench_regfile2.v
....\....\testbench_regfile3.v
....\....\testbench_regfile4.v
....\....\testbench_SimpleMemory.v
....\....\testbench_wd_reg.v
....\....\test_addr_reg.out
....\....\test_alu.out
....\....\test_barrel.out
....\....\test_booth.out
....\....\test_reg.out
....\....\test_regfile.out
....\....\test_wd_reg.out
....\....\wd_reg.v
....\arm7_core_design.pdf

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