VerilogHDL write with a RISC processor

compu1
......\.lso
......\Address_Register.v
......\Alu_RISC.v
......\compu.ise
......\compu.ise_ISE_Backup
......\compu.ntrc_log
......\Control_Unit.v
......\device_usage_statistics.html
......\D_flop.v
......\Instruction_Register.v
......\isim
......\....\work
......\....\....\glbl
......\....\....\....\glbl.h
......\....\....\....\mingw
......\....\....\....\.....\glbl.obj
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\testbench
......\....\....\.........\mingw
......\....\....\.........\.....\testbench.obj
......\....\....\.........\testbench.h
......\....\....\.........\xsimtestbench.cpp
......\....\....\testbench__v
......\....\....\............\mingw
......\....\....\............\.....\testbench__v.obj
......\....\....\............\testbench__v.h
......\....\....\............\xsimtestbench__v.cpp
......\....\....\vlg0A
......\....\....\.....\_address___register.bin
......\....\....\vlg0C
......\....\....\.....\_register___unit.bin
......\....\....\vlg18
......\....\....\.....\_r_i_s_c___s_p_m.bin
......\....\....\vlg24
......\....\....\.....\_control___unit.bin
......\....\....\.....\_multiplexer__3ch.bin
......\....\....\vlg2D
......\....\....\.....\glbl.bin
......\....\....\vlg3A
......\....\....\.....\_instruction___register.bin
......\....\....\vlg44
......\....\....\.....\_processing___unit.bin
......\....\....\vlg4B
......\....\....\.....\_program___counter.bin
......\....\....\vlg4C
......\....\....\.....\_memory___unit.bin
......\....\....\vlg56
......\....\....\.....\_multiplexer__5ch.bin
......\....\....\vlg5D
......\....\....\.....\testbench__v.bin
......\....\....\vlg6C
......\....\....\.....\testbench.bin
......\....\....\vlg6E
......\....\....\.....\_alu___r_i_s_c.bin
......\....\....\vlg78
......\....\....\.....\_d__flop.bin
......\....\....\_address___register
......\....\....\...................\mingw
......\....\....\...................\.....\_address___register.obj
......\....\....\...................\_address___register.h
......\....\....\_alu___r_i_s_c
......\....\....\..............\mingw
......\....\....\..............\.....\_alu___r_i_s_c.obj
......\....\....\..............\_alu___r_i_s_c.h
......\....\....\_control___unit
......\....\....\...............\mingw
......\....\....\...............\.....\_control___unit.obj
......\....\....\...............\_control___unit.h
......\....\....\_d__flop
......\....\....\........\mingw
......\....\....\........\.....\_d__flop.obj
......\....\....\........\_d__flop.h
......\....\....\_instruction___register
......\....\....\.......................\mingw
......\....\....\.......................\.....\_instruction___register.obj
......\....\....\.......................\_instruction___register.h
......\....\....\_memory___unit
......\....\....\..............\mingw
......\....\....\..............\.....\_memory___unit.obj
......\....\....\..............\xsim_memory___unit.cpp
......\....\....\..............\_memory___unit.h
......\....\....\_multiplexer__3ch
......\....\....\.................\mingw
......\....\....\.................\.....\_multiplexer__3ch.obj
......\....\....\.................\_multiplexer__3ch.h
......\....\....\_multiplexer__5ch
......\....\....\.................\mingw
......\....\....\.................\.....\_multiplexer__5ch.obj
......\....\....\.................\_multiplexer__5ch.h
......\....\....\_processing___unit
......\....\....\..................\mingw
......\....\....\..................\.....\_processing___unit.obj
......\....\....\..................\_processing___unit.h
......\....\....\_program___counter
......\....\....\..................\mingw
......\....\....\..................\.....\_program___counter.obj
......\....\....\..................\_program___counter.h
......\....\....\_register___unit

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