This is a communication signal that simulates SD protocol with the IO port of FPGA to realize the reading and writing program of SD, so long as the SD's CLK and SDATA are defined on the FPGA, the reading operation of SD can be completed

sdsource
........\SDExample
........\.........\SD
........\.........\..\sdcmd.c
........\.........\..\sdcmd.h
........\.........\..\sdcrc.c
........\.........\..\sdcrc.h
........\.........\..\sddriver.c
........\.........\..\sddriver.h
........\.........\..\sdhal.c
........\.........\..\sdhal.h
........\.........\SDExample.mcp
........\.........\src
........\.........\...\config.h
........\.........\...\IRQ.s
........\.........\...\LPC2294.h
........\.........\...\main.c
........\.........\...\mem_a.scf
........\.........\...\mem_b.scf
........\.........\...\mem_c.scf
........\.........\...\sdconfig.h
........\.........\...\Startup.s
........\.........\...\target.c
........\.........\...\target.h
........\.........\uart
........\.........\....\uart.c
........\.........\....\uart.h
........\SD卡读写模块
........\............\SD
........\............\..\sdcmd.c
........\............\..\sdcmd.h
........\............\..\sdcrc.c
........\............\..\sdcrc.h
........\............\..\sddriver.c
........\............\..\sddriver.h
........\............\..\sdhal.c
........\............\..\sdhal.h
........\............\sdconfig.h
........\............\使用说明.txt

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