Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the simple requirements of frequency measurement

Freq
....\Control.bsf
....\Control.v
....\Control.vwf
....\Counter.bsf
....\Counter.v
....\Counter.vwf
....\db
....\..\Freq.asm.qmsg
....\..\Freq.cbx.xml
....\..\Freq.cmp.cdb
....\..\Freq.cmp.hdb
....\..\Freq.cmp.kpt
....\..\Freq.cmp.logdb
....\..\Freq.cmp.rdb
....\..\Freq.cmp.tdb
....\..\Freq.cmp0.ddb
....\..\Freq.dbp
....\..\Freq.db_info
....\..\Freq.eco.cdb
....\..\Freq.eds_overflow
....\..\Freq.fit.qmsg
....\..\Freq.hier_info
....\..\Freq.hif
....\..\Freq.map.cdb
....\..\Freq.map.hdb
....\..\Freq.map.logdb
....\..\Freq.map.qmsg
....\..\Freq.pre_map.cdb
....\..\Freq.pre_map.hdb
....\..\Freq.psp
....\..\Freq.rtlv.hdb
....\..\Freq.rtlv_sg.cdb
....\..\Freq.rtlv_sg_swap.cdb
....\..\Freq.sgdiff.cdb
....\..\Freq.sgdiff.hdb
....\..\Freq.signalprobe.cdb
....\..\Freq.sim.hdb
....\..\Freq.sim.qmsg
....\..\Freq.sim.rdb
....\..\Freq.sim.vwf
....\..\Freq.sld_design_entry.sci
....\..\Freq.sld_design_entry_dsc.sci
....\..\Freq.smp_dump.txt
....\..\Freq.syn_hier_info
....\..\Freq.tan.qmsg
....\..\wed.zsf
....\Display.bsf
....\Display.v
....\DivFreq.bsf
....\DivFreq.v
....\Freq.asm.rpt
....\Freq.bdf
....\Freq.done
....\Freq.fit.rpt
....\Freq.fit.smsg
....\Freq.fit.summary
....\Freq.flow.rpt
....\Freq.map.rpt
....\Freq.map.smsg
....\Freq.map.summary
....\Freq.pin
....\Freq.pof
....\Freq.qpf
....\Freq.qsf
....\Freq.qws
....\Freq.sim.rpt
....\Freq.sof
....\Freq.tan.rpt
....\Freq.tan.summary
....\Freq.vwf
....\Lock.bsf
....\Lock.v

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