Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic

digtalclk
.........\bin2seg.bsf
.........\bin2seg.v
.........\clock.bsf
.........\clock.v
.........\cmp_state.ini
.........\db
.........\..\add_sub_2rh.tdf
.........\..\add_sub_3c8.tdf
.........\..\add_sub_4g8.tdf
.........\..\add_sub_4rh.tdf
.........\..\add_sub_5g8.tdf
.........\..\add_sub_5rh.tdf
.........\..\add_sub_6rh.tdf
.........\..\add_sub_7rh.tdf
.........\..\add_sub_ke8.tdf
.........\..\add_sub_le8.tdf
.........\..\add_sub_lsh.tdf
.........\..\add_sub_ma8.tdf
.........\..\add_sub_me8.tdf
.........\..\add_sub_ne8.tdf
.........\..\add_sub_oe8.tdf
.........\..\add_sub_pa8.tdf
.........\..\add_sub_pe8.tdf
.........\..\add_sub_qe8.tdf
.........\..\add_sub_ra8.tdf
.........\..\add_sub_re8.tdf
.........\..\add_sub_se8.tdf
.........\..\alt_u_div_5rd.tdf
.........\..\alt_u_div_bld.tdf
.........\..\alt_u_div_bod.tdf
.........\..\alt_u_div_dld.tdf
.........\..\alt_u_div_fld.tdf
.........\..\alt_u_div_hod.tdf
.........\..\alt_u_div_lod.tdf
.........\..\cntr_gu8.tdf
.........\..\decode_m0b.tdf
.........\..\digtalclk.asm.qmsg
.........\..\digtalclk.cbx.xml
.........\..\digtalclk.cmp.cdb
.........\..\digtalclk.cmp.hdb
.........\..\digtalclk.cmp.rdb
.........\..\digtalclk.cmp.tdb
.........\..\digtalclk.cmp0.ddb
.........\..\digtalclk.db_info
.........\..\digtalclk.eco.cdb
.........\..\digtalclk.eds_overflow
.........\..\digtalclk.fit.qmsg
.........\..\digtalclk.fnsim.hdb
.........\..\digtalclk.hier_info
.........\..\digtalclk.hif
.........\..\digtalclk.map.cdb
.........\..\digtalclk.map.hdb
.........\..\digtalclk.map.qmsg
.........\..\digtalclk.pre_map.cdb
.........\..\digtalclk.pre_map.hdb
.........\..\digtalclk.psp
.........\..\digtalclk.rtlv.hdb
.........\..\digtalclk.rtlv_sg.cdb
.........\..\digtalclk.rtlv_sg_swap.cdb
.........\..\digtalclk.sgdiff.cdb
.........\..\digtalclk.sgdiff.hdb
.........\..\digtalclk.signalprobe.cdb
.........\..\digtalclk.sim.hdb
.........\..\digtalclk.sim.qmsg
.........\..\digtalclk.sim.rdb
.........\..\digtalclk.sim.vwf
.........\..\digtalclk.sld_design_entry.sci
.........\..\digtalclk.sld_design_entry_dsc.sci
.........\..\digtalclk.syn_hier_info
.........\..\digtalclk.tan.qmsg
.........\..\digtalclk_cmp.qrpt
.........\..\digtalclk_sim.qrpt
.........\..\lpm_divide_1nf.tdf
.........\..\lpm_divide_4ff.tdf
.........\..\lpm_divide_4nf.tdf
.........\..\lpm_divide_6nf.tdf
.........\..\lpm_divide_eof.tdf
.........\..\lpm_divide_hlf.tdf
.........\..\lpm_divide_ilf.tdf
.........\..\lpm_divide_jlf.tdf
.........\..\lpm_divide_kdf.tdf
.........\..\lpm_divide_ldf.tdf
.........\..\lpm_divide_mdf.tdf
.........\..\mux_9fc.tdf
.........\..\sign_div_unsign_3jg.tdf
.........\..\sign_div_unsign_6jg.tdf
.........\..\sign_div_unsign_8jg.tdf
.........\..\sign_div_unsign_gkg.tdf
.........\..\sign_div_unsign_jhg.tdf
.........\..\sign_div_unsign_khg.tdf
.........\..\sign_div_unsign_lhg.tdf
.........\digtalclk.asm.rpt
.........\digtalclk.bdf
.........\digtalclk.cdf
.........\digtalclk.done
.........\digtalclk.fit.eqn
.........\digtalclk.fit.rpt
.........\digtalclk.fit.summary
.........\digtalclk.flow.rpt

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