CPLD with minimal resources, using Verilog in QuartusII7.1 to achieve the 1280 frequency.

Filename	Size	Update
clkgen
......\clkgen	RTL Viewer.pdf
......\clkgen.asm.rpt
......\clkgen.done
......\clkgen.dpf
......\clkgen.fit.rpt
......\clkgen.fit.smsg
......\clkgen.fit.summary
......\clkgen.flow.rpt
......\clkgen.map.rpt
......\clkgen.map.smsg
......\clkgen.map.summary
......\clkgen.pin
......\clkgen.pof
......\clkgen.qpf
......\clkgen.qsf
......\clkgen.qws
......\clkgen.sdc
......\clkgen.sim	Functional.pdf
......\clkgen.sim	Timing.pdf
......\clkgen.sim.rpt
......\clkgen.sta.rpt
......\clkgen.sta.summary
......\clkgen.tan.rpt
......\clkgen.tan.summary
......\clkgen.v
......\clkgen.v.bak
......\clkgen.vwf
......\db
......\..\add_sub_e7c.tdf
......\..\add_sub_elh.tdf
......\..\add_sub_f3c.tdf
......\..\add_sub_f7c.tdf
......\..\add_sub_flh.tdf
......\..\add_sub_g7c.tdf
......\..\add_sub_jlh.tdf
......\..\alt_u_div_5ie.tdf
......\..\clkgen.asm.qmsg
......\..\clkgen.asm_labs.ddb
......\..\clkgen.cbx.xml
......\..\clkgen.cmp.cdb
......\..\clkgen.cmp.hdb
......\..\clkgen.cmp.logdb
......\..\clkgen.cmp.rdb
......\..\clkgen.cmp.tdb
......\..\clkgen.cmp0.ddb
......\..\clkgen.dbp
......\..\clkgen.db_info
......\..\clkgen.eco.cdb
......\..\clkgen.eds_overflow
......\..\clkgen.fit.qmsg
......\..\clkgen.fnsim.hdb
......\..\clkgen.fnsim.qmsg
......\..\clkgen.hier_info
......\..\clkgen.hif
......\..\clkgen.map.cdb
......\..\clkgen.map.hdb
......\..\clkgen.map.logdb
......\..\clkgen.map.qmsg
......\..\clkgen.pre_map.cdb
......\..\clkgen.pre_map.hdb
......\..\clkgen.psp
......\..\clkgen.pss
......\..\clkgen.rpp.qmsg
......\..\clkgen.rtlv.hdb
......\..\clkgen.rtlv_sg.cdb
......\..\clkgen.rtlv_sg_swap.cdb
......\..\clkgen.sgate.rvd
......\..\clkgen.sgate_sm.rvd
......\..\clkgen.sgdiff.cdb
......\..\clkgen.sgdiff.hdb
......\..\clkgen.signalprobe.cdb
......\..\clkgen.sim.cvwf
......\..\clkgen.sim.hdb
......\..\clkgen.sim.qmsg
......\..\clkgen.sim.qrpt
......\..\clkgen.sim.rdb
......\..\clkgen.sld_design_entry.sci
......\..\clkgen.sld_design_entry_dsc.sci
......\..\clkgen.sta.qmsg
......\..\clkgen.sta.rdb
......\..\clkgen.syn_hier_info
......\..\clkgen.tan.qmsg
......\..\lpm_divide_nnl.tdf
......\..\prev_cmp_clkgen.asm.qmsg
......\..\prev_cmp_clkgen.fit.qmsg
......\..\prev_cmp_clkgen.map.qmsg
......\..\prev_cmp_clkgen.sim.qmsg
......\..\prev_cmp_clkgen.sta.qmsg
......\..\prev_cmp_clkgen.tan.qmsg
......\..\sign_div_unsign_5kh.tdf
......\..\wed.wsf
......\prev_cmp_clkgen.qmsg
......\undo_redo.txt

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