integrity of the connection of FPGA and debug source code, the map is DSN format, it can directly dragged into PROTEL Lane open.

Packet : 13898362xilinx_fpga_design&code.rar filelist
XCS2000
XCS2000\spartanII.PCB
XCS2000\SPARII.OLB
XCS2000\SPANTANII.DSN

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