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Packet : 81404609sram_verilog.rar filelist
sram_verilog\sram.qpf
sram_verilog\sram.qsf
sram_verilog\db\cntr_qed.tdf
sram_verilog\db\sram.db_info
sram_verilog\db\sram.map.qmsg
sram_verilog\db\sram.cmp.rdb
sram_verilog\db\sram.sld_design_entry.sci
sram_verilog\db\sram.eco.cdb
sram_verilog\db\sram.(0).cnf.cdb
sram_verilog\db\sram.(0).cnf.hdb
sram_verilog\db\sram.rtlv.hdb
sram_verilog\db\sram.fnsim.qmsg
sram_verilog\db\sram.cmp.qrpt
sram_verilog\db\sram.cbx.xml
sram_verilog\db\sram.hif
sram_verilog\db\sram.analyze_file.qmsg
sram_verilog\db\sram.(2).cnf.cdb
sram_verilog\db\sram.sim.qmsg
sram_verilog\db\sram.(2).cnf.hdb
sram_verilog\db\sram.(1).cnf.cdb
sram_verilog\db\sram.(3).cnf.cdb
sram_verilog\db\sram.sim.hdb
sram_verilog\db\sram.(1).cnf.hdb
sram_verilog\db\sram.(3).cnf.hdb
sram_verilog\db\add_sub_nsh.tdf
sram_verilog\db\sram.sim.rdb
sram_verilog\db\sram.eds_overflow
sram_verilog\db\sram.rtlv_sg.cdb
sram_verilog\db\sram.rtlv_sg_swap.cdb
sram_verilog\db\sram.sim.qrpt
sram_verilog\db\sram.pre_map.cdb
sram_verilog\db\sram.sgdiff.hdb
sram_verilog\db\sram.pre_map.hdb
sram_verilog\db\sram.sgdiff.cdb
sram_verilog\db\sram.sld_design_entry_dsc.sci
sram_verilog\db\sram.(4).cnf.cdb
sram_verilog\db\sram.(4).cnf.hdb
sram_verilog\db\altsyncram_tnr.tdf
sram_verilog\db\sram.(5).cnf.cdb
sram_verilog\db\sram.(5).cnf.hdb
sram_verilog\db\sram.(6).cnf.cdb
sram_verilog\db\sram.(6).cnf.hdb
sram_verilog\db\sram.(7).cnf.cdb
sram_verilog\db\sram.(7).cnf.hdb
sram_verilog\db\sram.(8).cnf.cdb
sram_verilog\db\sram.(8).cnf.hdb
sram_verilog\db\sram.(9).cnf.cdb
sram_verilog\db\sram.(9).cnf.hdb
sram_verilog\db\sram.map.cdb
sram_verilog\db\sram.map.hdb
sram_verilog\db\sram.fnsim.hdb
sram_verilog\db\sram.hier_info
sram_verilog\db\sram.psp
sram_verilog\db\sram.dbp
sram_verilog\db\sram.syn_hier_info
sram_verilog\db
sram_verilog\SRAM.vwf
sram_verilog\SRAM.v
sram_verilog\sram.map.rpt
sram_verilog\sram.flow.rpt
sram_verilog\sram.map.summary
sram_verilog\SRAM_WR.v
sram_verilog\SRAM_RD.v
sram_verilog\undo_redo.txt
sram_verilog\serv_req_info.txt
sram_verilog\sram.map.eqn
sram_verilog\sram.done
sram_verilog\sram.sim.rpt
sram_verilog\M65535.vwf
sram_verilog\M65536.v
sram_verilog\sram.qws
sram_verilog\SRAM_RD.vwf
sram_verilog\SRAM_WR.bsf
sram_verilog\SRAM_RD.bsf
sram_verilog\rom.mif
sram_verilog\conter1_waveforms.html
sram_verilog\conter1_wave0.jpg
sram_verilog\conter1.v
sram_verilog\conter1.bsf
sram_verilog\SRAM.bdf
sram_verilog\ROM.v
sram_verilog\ROM.bsf
sram_verilog\mybus.v
sram_verilog\mybus.bsf
sram_verilog