VHDL source code development environment: MAXPLUS II 10.2

CPLD程序
........\K_ZP_RJ_D103_60
........\...............\dual_ram_gdf.acf
........\...............\dual_ram_gdf.fit
........\...............\dual_ram_gdf.gdf
........\...............\dual_ram_gdf.hif
........\...............\dual_ram_gdf.inc
........\...............\dual_ram_gdf.jam
........\...............\dual_ram_gdf.jbc
........\...............\dual_ram_gdf.mmf
........\...............\dual_ram_gdf.ndb
........\...............\dual_ram_gdf.pin
........\...............\dual_ram_gdf.pof
........\...............\dual_ram_gdf.rpt
........\...............\dual_ram_gdf.scf
........\...............\dual_ram_gdf.snf
........\...............\dual_ram_gdf.sym
........\...............\引脚图.txt

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