The DCT of source code Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA

CLKGEN.VHD
COMPILE.do
COMPILE_Q.DO
COMPILE_R.do
COMPILE_S.DO
COMPILE_Z.DO
divider.cr.mti
divider.mpf
divider.vhd
DIVIDER_TB.VHD
FIFO.vhd
precision.log
project_1.psp
QUANTIZER.vhd
QUANTIZER_TB.vhd
RAMZ.VHD
random1.vhd
report.txt
RLE.VHD
RLE_PKG.VHD
RLE_TB.VHD
ROMQ.vhd
RUNSIM.DO
RUNSIM_Q.DO
RUNSIM_R.DO
RUNSIM_S.DO
RUNSIM_Z.DO
s_divider.vhd
S_DIVIDER_TB.vhd
wave.do
wave_q.do
wave_r.do
wave_s.do
wave_z.do
ZIGZAG.VHD
ZIGZAG_TB.vhd

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