Introduction - If you have any usage issues, please Google them yourself
that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Packet : 51622466ddr_verilog_xilinx.zip filelist
define.v
glbl.v
mt46v4m16.v
readme.txt
string_decode_fn.v
tb_top.v
top.ucf
top_func.v