spi bus controller realize the FPGA Verilog source code and test

SimpleSpi
.........\Bench
.........\.....\spi_slave_model.v
.........\.....\tst_bench_top.v
.........\.....\wb_master_model.v
.........\doc
.........\...\simple_spi.doc
.........\...\simple_spi.pdf
.........\Rtl
.........\...\fifo4.v
.........\...\simple_spi_top.v
.........\sim
.........\...\bin
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\run
.........\...\...\Makefile.1;content-type=text%2Fplain.txt
.........\...\...\ncsim.log
.........\...\...\ncvlog.log
.........\...\...\simvision.sv.txt
.........\...\...\stdout.log
.........\...\...\waves.do.txt

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