a verilog prigram for SPI

spi_coolrunner_ver3
...................\clk_gen.v
...................\counter_4bit.v
...................\counter_5bit.v
...................\mcu_interface.v
...................\rec_shift.v
...................\rev_1
...................\.....\AutoConstraint_spi_master_interface_bt_top.sdc
...................\.....\spi_master_interface_bt_top.edf
...................\.....\spi_master_interface_bt_top.fse
...................\.....\spi_master_interface_bt_top.ncf
...................\.....\spi_master_interface_bt_top.srd
...................\.....\spi_master_interface_bt_top.srm
...................\.....\spi_master_interface_bt_top.srr
...................\.....\spi_master_interface_bt_top.srs
...................\.....\spi_master_interface_bt_top.tlg
...................\.....\syntmp
...................\.....\......\spi_master_interface_bt_top.plg
...................\.....\......\tx_shift.plg
...................\.....\tx_shift.edf
...................\.....\tx_shift.fse
...................\.....\tx_shift.ncf
...................\.....\tx_shift.srd
...................\.....\tx_shift.srm
...................\.....\tx_shift.srr
...................\.....\tx_shift.srs
...................\.....\tx_shift.tlg
...................\spi_controller.v
...................\spi_interface.v
...................\spi_master.v
...................\spi_master_interface.v
...................\spi_master_interface_bt.v
...................\spi_master_interface_bt_top.v
...................\spi_master_interface_bt_top_tb.v
...................\spi_t.prd
...................\spi_t.prj
...................\state_controller.v
...................\state_controller_top.v
...................\tx_shift.v

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