5牟 水 撸 朔 一 虻サ 卸蔚 统 一卸危摹 蔚 统 桑 偌 一要 说 一CPU品一些 虻サ 模 臃 朔

32位CPU设计
...........\CPU设计报告.doc
...........\Super
...........\.....\Adder
...........\.....\.....\Adder.v
...........\.....\Adder32.v
...........\.....\ALU.v
...........\.....\CtrlUnit.v
...........\.....\Decoder
...........\.....\.......\Decoder.v
...........\.....\FlagReg.v
...........\.....\GET_OPER.v
...........\.....\IMME_EX.v
...........\.....\INS_DECODER.v
...........\.....\IRLoader.v
...........\.....\J_PATH.v
...........\.....\Logic
...........\.....\.....\Logic32.v
...........\.....\Mul16.v
...........\.....\MUX
...........\.....\...\MUX32x32.v
...........\.....\...\MUXx1.v
...........\.....\...\MUXx1test.v
...........\.....\MUXx1.v
...........\.....\Ram.v
...........\.....\Reg32
...........\.....\.....\D_flp.v
...........\.....\.....\Reg32.v
...........\.....\.....\RegGroup32.v
...........\.....\Reg32.v
...........\.....\RegGroup32.v
...........\.....\Relative
...........\.....\........\MUXx1.v
...........\.....\........\Relative.v
...........\.....\Shift32
...........\.....\.......\Inc5.v
...........\.....\.......\Shift32.v
...........\.....\.......\Shift64_32.v
...........\.....\Super.v
...........\.....\SysIns.v
...........\.....\test.txt
...........\.....\work
...........\.....\....\@a@l@u
...........\.....\....\......\verilog.asm
...........\.....\....\......\_primary.dat
...........\.....\....\......\_primary.vhd
...........\.....\....\@adder16_@m
...........\.....\....\...........\verilog.asm
...........\.....\....\...........\_primary.dat
...........\.....\....\...........\_primary.vhd
...........\.....\....\@adder32
...........\.....\....\........\verilog.asm
...........\.....\....\........\_primary.dat
...........\.....\....\........\_primary.vhd
...........\.....\....\@adder4x8
...........\.....\....\.........\verilog.asm
...........\.....\....\.........\_primary.dat
...........\.....\....\.........\_primary.vhd
...........\.....\....\@adder4_@m
...........\.....\....\..........\verilog.asm
...........\.....\....\..........\_primary.dat
...........\.....\....\..........\_primary.vhd
...........\.....\....\@adder8
...........\.....\....\.......\verilog.asm
...........\.....\....\.......\_primary.dat
...........\.....\....\.......\_primary.vhd
...........\.....\....\@block
...........\.....\....\......\verilog.asm
...........\.....\....\......\_primary.dat
...........\.....\....\......\_primary.vhd
...........\.....\....\@compare5
...........\.....\....\.........\verilog.asm
...........\.....\....\.........\_primary.dat
...........\.....\....\.........\_primary.vhd
...........\.....\....\@ctrl@unit
...........\.....\....\..........\verilog.asm
...........\.....\....\..........\_primary.dat
...........\.....\....\..........\_primary.vhd
...........\.....\....\@dec2
...........\.....\....\.....\verilog.asm
...........\.....\....\.....\_primary.dat
...........\.....\....\.....\_primary.vhd
...........\.....\....\@dec3
...........\.....\....\.....\verilog.asm
...........\.....\....\.....\_primary.dat
...........\.....\....\.....\_primary.vhd
...........\.....\....\@dec32
...........\.....\....\......\verilog.asm
...........\.....\....\......\_primary.dat
...........\.....\....\......\_primary.vhd
...........\.....\....\@does1@read
...........\.....\....\...........\verilog.asm
...........\.....\....\...........\_primary.dat
...........\.....\....\...........\_primary.vhd
...........\.....\....\@does@write
...........\.....\....\...........\verilog.asm
...........\.....\....\...........\_primary.dat
...........\.....\....\...........\_primary.vhd
...........\.....\....\@d_flipflop
...........\.....\....\...........\verilog.asm

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