Introduction - If you have any usage issues, please Google them yourself
this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Packet : 55593364wavegenerator_testbench.rar filelist
测试向量和波形发生器\8bit采样sine波形发生器.txt
测试向量和波形发生器\加法器源程序.v
测试向量和波形发生器\相应加法器的测试向量(test bench).v
测试向量和波形发生器\transcript
测试向量和波形发生器