In ccs debug DSP external memory sdram of the anti-color code, mainly through the dsp / bios in the HST pipeline implementation. One choice is the DM642 chip and MT48LC16M16A2 the sdram, sdram and the related timing parameters have been configured.

reversalBW64_7.10
.................\cc_build_Debug.log
.................\Debug
.................\Debug.lkf
.................\Debug.lkv
.................\rBW.cdb
.................\rBWcfg.cmd
.................\rBWcfg.h
.................\rBWcfg.h62
.................\rBWcfg.s62
.................\rBWcfg_c.c
.................\rBWmain.c
.................\rBWmain.c.bak
.................\reversalBW.CS_
.................\..............\FILE.CDX
.................\..............\FILE.DBF
.................\..............\FILE.FPT
.................\..............\SYMBOL.CDX
.................\..............\SYMBOL.DBF
.................\..............\SYMBOL.FPT
.................\reversalBW.paf
.................\reversalBW.paf2
.................\reversalBW.pjt
.................\reversalBW.sbl

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