The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.

DDS
...\ADDER10B.vhd
...\ADDER32B.vhd
...\data.mif
...\db
...\..\altsyncram_3mi2.tdf
...\..\altsyncram_4f51.tdf
...\..\altsyncram_bbj2.tdf
...\..\altsyncram_ff51.tdf
...\..\altsyncram_mbj2.tdf
...\..\cmpr_fnh.tdf
...\..\cntr_5af.tdf
...\..\cntr_8he.tdf
...\..\cntr_dkf.tdf
...\..\cntr_ebg.tdf
...\..\cntr_fgh.tdf
...\..\DDS.asm.qmsg
...\..\DDS.cbx.xml
...\..\DDS.cmp.cdb
...\..\DDS.cmp.hdb
...\..\DDS.cmp.kpt
...\..\DDS.cmp.logdb
...\..\DDS.cmp.rdb
...\..\DDS.cmp.tdb
...\..\DDS.cmp0.ddb
...\..\DDS.dbp
...\..\DDS.db_info
...\..\DDS.eco.cdb
...\..\DDS.eds_overflow
...\..\DDS.fit.qmsg
...\..\DDS.hier_info
...\..\DDS.hif
...\..\DDS.map.cdb
...\..\DDS.map.hdb
...\..\DDS.map.logdb
...\..\DDS.map.qmsg
...\..\DDS.pre_map.cdb
...\..\DDS.pre_map.hdb
...\..\DDS.psp
...\..\DDS.rtlv.hdb
...\..\DDS.rtlv_sg.cdb
...\..\DDS.rtlv_sg_swap.cdb
...\..\DDS.sgdiff.cdb
...\..\DDS.sgdiff.hdb
...\..\DDS.signalprobe.cdb
...\..\DDS.sim.hdb
...\..\DDS.sim.qmsg
...\..\DDS.sim.rdb
...\..\DDS.sim_ori.vwf
...\..\DDS.sld_design_entry.sci
...\..\DDS.sld_design_entry_dsc.sci
...\..\DDS.syn_hier_info
...\..\DDS.tan.qmsg
...\..\decode_ogi.tdf
...\..\wed.zsf
...\DDS.asm.rpt
...\DDS.done
...\DDS.fit.rpt
...\DDS.fit.smsg
...\DDS.fit.summary
...\DDS.flow.rpt
...\DDS.map.rpt
...\DDS.map.summary
...\DDS.pin
...\DDS.pof
...\DDS.qpf
...\DDS.qsf
...\DDS.qws
...\DDS.sim.rpt
...\DDS.sof
...\DDS.tan.rpt
...\DDS.tan.summary
...\DDS.vhd
...\DDS.vwf
...\LCD.vhd
...\REG10B.vhd
...\REG32B.vhd
...\SIN_ROM.cmp
...\SIN_ROM.vhd
...\sin_rom_10.mif
...\sopc_builder_debug_log.txt
...\stp1.stp

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．