Verilog language, nios minimum system, tested successfully in the DE2 board

readme.txt
sys_nios
........\ce_temp_directory
........\cpu_0.ocp
........\cpu_0.v
........\cpu_0.vo
........\cpu_0_bht_ram.mif
........\cpu_0_dc_tag_ram.mif
........\cpu_0_ic_tag_ram.mif
........\cpu_0_jtag_debug_module.v
........\cpu_0_jtag_debug_module_wrapper.v
........\cpu_0_mult_cell.v
........\cpu_0_ociram_default_contents.mif
........\cpu_0_rf_ram_a.mif
........\cpu_0_rf_ram_b.mif
........\cpu_0_test_bench.v
........\db
........\..\altsyncram_4be1.tdf
........\..\altsyncram_5be1.tdf
........\..\altsyncram_a422.tdf
........\..\altsyncram_bie1.tdf
........\..\altsyncram_c572.tdf
........\..\altsyncram_cub1.tdf
........\..\altsyncram_e502.tdf
........\..\altsyncram_k1l1.tdf
........\..\altsyncram_pfn1.tdf
........\..\altsyncram_q7a1.tdf
........\..\altsyncram_q8e1.tdf
........\..\altsyncram_rc22.tdf
........\..\decode_aoi.tdf
........\..\ded_mult_2o81.tdf
........\..\dffpipe_93c.tdf
........\..\mult_add_4cr2.tdf
........\..\mult_add_6cr2.tdf
........\..\sys.asm.qmsg
........\..\sys.asm_labs.ddb
........\..\sys.cbx.xml
........\..\sys.cmp.cdb
........\..\sys.cmp.hdb
........\..\sys.cmp.kpt
........\..\sys.cmp.logdb
........\..\sys.cmp.rdb
........\..\sys.cmp.tdb
........\..\sys.cmp0.ddb
........\..\sys.dbp
........\..\sys.db_info
........\..\sys.eco.cdb
........\..\sys.fit.qmsg
........\..\sys.hier_info
........\..\sys.hif
........\..\sys.map.cdb
........\..\sys.map.hdb
........\..\sys.map.logdb
........\..\sys.map.qmsg
........\..\sys.pre_map.cdb
........\..\sys.pre_map.hdb
........\..\sys.psp
........\..\sys.rtlv.hdb
........\..\sys.rtlv_sg.cdb
........\..\sys.rtlv_sg_swap.cdb
........\..\sys.sgdiff.cdb
........\..\sys.sgdiff.hdb
........\..\sys.signalprobe.cdb
........\..\sys.sld_design_entry.sci
........\..\sys.sld_design_entry_dsc.sci
........\..\sys.smp_dump.txt
........\..\sys.syn_hier_info
........\..\sys.tan.qmsg
........\hello_led_0
........\...........\.cdtbuild
........\...........\.cdtproject
........\...........\.project
........\...........\application.stf
........\...........\Debug
........\...........\hello_led.c
........\...........\readme.txt
........\hello_led_0_syslib
........\..................\.cdtbuild
........\..................\.cdtproject
........\..................\.project
........\..................\Debug
........\..................\readme.txt
........\..................\system.stf
........\LED_GREEN.v
........\nios_0.bsf
........\nios_0.ptf
........\nios_0.ptf.bak
........\nios_0.v
........\nios_0_generation_script
........\nios_0_log.txt
........\nios_0_setup_quartus.tcl
........\nios_0_sim
........\..........\cpu_0_bht_ram.dat
........\..........\cpu_0_bht_ram.hex
........\..........\cpu_0_dc_tag_ram.dat
........\..........\cpu_0_dc_tag_ram.hex
........\..........\cpu_0_ic_tag_ram.dat
........\..........\cpu_0_ic_tag_ram.hex
........\..........\cpu_0_ociram_default_contents.dat
........\..........\cpu_0_ociram_default_contents.hex

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