Introduction - If you have any usage issues, please Google them yourself
on display in Chinese characters, achieving the FPGA, using Verilog HDL design, However, the use of direct completely
Packet : 29782200vgachinese.rar filelist
Release\vga_test1.bit
Release\char_rom_c.V
Release\sync_gen_50m.v
Release\vga_test1.v
Release\vga_test1_ucf.ucf
Release