TMS3205402Verilog HDL source

cpld2
.....\.untf
.....\actgen
.....\automake.log
.....\constraint
.....\coreconsole
.....\cpld.dhp
.....\cpld.ise
.....\cpld.ise_ISE_Backup
.....\cpld.ptf
.....\cpld_ise6_bak.zip
.....\designer
.....\........\convert.log
.....\........\convert.tcl
.....\........\impl1
.....\........\.....\impl.prj_des
.....\........\.....\simulation
.....\hdl
.....\my.ana
.....\my.bld
.....\my.cmd_log
.....\my.convert.sav
.....\my.data
.....\my.gyd
.....\my.imp
.....\my.jed
.....\my.lso
.....\my.mfd
.....\my.mod
.....\my.ngc
.....\my.ngd
.....\my.ngr
.....\my.pad
.....\my.pnx
.....\my.prj
.....\my.rpt
.....\my.sprj
.....\my.stx
.....\my.syr
.....\my.tim
.....\my.tspec
.....\my.v
.....\my.vm6
.....\my.xml
.....\my._hrpt
.....\my_build.xml
.....\my_cpld_cfg.cdf
.....\my_html
.....\.......\fit
.....\.......\...\applet.htm
.....\.......\...\applet.js
.....\.......\...\appletref.htm
.....\.......\...\ascii.htm
.....\.......\...\ascii.tmp
.....\.......\...\asciidoc.htm

.....\.......\...\beginstraight.gif
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.....\.......\...\check.htm
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