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Description: C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
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Size: 24576 |
Author: 蔡科 |
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Description: implement a Hopfield network for the retrieval of stored 2-D patterns-Input Parameters: Ask the user to input the number of fundamental memories p (2 ≤ p ≤ 5), the width w (3 ≤ w
≤ 5) and height h (3 ≤ h ≤ 6) of each 2-D pattern.
Storage Phase: Each fundamental memory is stored in a text file with .txt extension.
Retrieval Phase: Ask the user to input the name of the text file storing the noisy pattern.
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Size: 4096 |
Author: Owen Yin |
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Description: 给出了不同分割数量V条件下的系统的PAPR性能，分割方法为随机分割，辅助相位集合的相位数P=4(即 可选择的范围为{0,π/2,π,3π/4})，N=128，子载波采用QPSK调制，仿真的OFDM符号数为1000个。-V gives the number of different partitions of the system under PAPR performance of random segmentation segmentation, the number of secondary phase of the phase set P = 4 (to select the range {0, π/2, π, 3π/4} ), N = 128, sub-carrier using QPSK modulation, simulation of the OFDM symbol number 1000.
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Size: 1024 |
Author: 宫约 |
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Description: 基于labVIEW的三相电流不平衡度测试-LabVIEW:three-phase current imbalance degree test
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Size: 17408 |
Author: 单俊 |
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Description: 基于labVIEW的三相电路有效值测试-LabVIEW:effective value of three-phase circuit
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Size: 9216 |
Author: 单俊 |
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Description: 基于labVIEW的三相电路谐波测试软件-LabVIEW：harmonic test of three-phase circuit
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Size: 16384 |
Author: 单俊 |
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Description: 基于labVIEW的三相电路的功率测试软件-LabVIEW：three-phase power test
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Size: 16384 |
Author: 单俊 |
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Description: disign whit HSPICE:
Design and simulate a two stage CMOS operational amplifier shown in the Fig., for these
conditions:
DC Voltage Gain > 60dB
Unity Gain Bandwidth > 70MHz
Phase Margin > 50 degrees
Power Dissipation: as low as possible
Technology: 2μm
Power Supply: 3.3V
Load Capacitance: 2pF
Output Voltage Swing > 2Vp-p
Make a unity feedback buffer and check the settling time of the circuit when you inject
a step voltage to the input with rise and fall time of 1μs.
Document your results in a written report including design procedure and all of
simulations. You also should highlight the most important features of the design.-disign whit HSPICE:
Design and simulate a two stage CMOS operational amplifier shown in the Fig., for these
conditions:
DC Voltage Gain > 60dB
Unity Gain Bandwidth > 70MHz
Phase Margin > 50 degrees
Power Dissipation: as low as possible
Technology: 2μm
Power Supply: 3.3V
Load Capacitance: 2pF
Output Voltage Swing > 2Vp-p
Make a unity feedback buffer and check the settling time of the circuit when you inject
a step voltage to the input with rise and fall time of 1μs.
Document your results in a written report including design procedure and all of
simulations. You also should highlight the most important features of the design.
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Size: 47104 |
Author: jack |
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Description: 功能[DATAOUT]= PGA（DATAIN），执行相位梯度
％ISAR自动对焦。
％
％DATAIN ISAR范围内的实时数据。
DATAOUT％范围内的实时数据已被删除平移
％相位误差。
％
％参考：
％D.E.瓦尔，P.H.艾歇尔，特区吉利亚，C.V. Jakowatz，“相
％梯度自聚焦一个强大的工具，用于高分辨率SAR相
％修正“，硕士论文。航空。＆电子系统，第30卷，3，1994。-function [dataout]=PGA(datain) performs phase gradient
autofocus of ISAR.
datain is range-time data of ISAR.
dataout is range-time data that have been removed translational
phase error.
Reference:
D.E. Wahl, P.H. Eichel, D.C. Ghiglia, C.V. Jakowatz, "Phase
gradient autofocus-a robust tool for high resolution SAR phase
correction," IEEE Trans. Aero. & Elec. Sys., vol. 30, no. 3, 1994.
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Size: 1024 |
Author: laureatew |
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Description: 通过SMBUS传递步进电机运转参数，电机驱动可以任意2相4拍，3相6拍等，加速步数，运转步数，高速运转，停止。-
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取消
Tōngguò SMBUS chuándì bù jìn diànjī yùnzhuǎn shēn shù, diànjī qūdòng kěyǐ rènyì 2 xiāng 4 pāi,3 xiāng 6 pāi děng, jiāsù bù shù, yùnzhuǎn bù shù, gāosù yùnzhuǎn, tíngzhǐ. .Passing through SMBUS stepper motor operating parameters, the motor drive can be any two-phase 4-shot, 3-phase 6 shot, etc., to accelerate the number of steps, running steps, high speed, stop.
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Size: 6144 |
Author: bai zheng qiang |
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Description: 该BTN8960TA是NovalithIC™ 系列包含在一个封装中三个独立的芯片组成部分：一个P沟道
高侧MOSFET和一个n沟道低侧MOSFET一起的驱动器IC，从而形成一个集成的高
当前半桥。所有的三个芯片安装在一个公共引线框架，使用由上芯片和芯片的芯片
芯片技术。电源开关采用垂直MOS技术，以确保最佳的导通电阻。
由于p沟道高侧切换需要一个电荷泵从而消除了最小的EMI。 界面
以微控制器是由容易被集成驱动器IC哪些功能逻辑电平输入，诊断
电流检测，转换率的调整，死区时间生成和防止过热，欠压，
过流和短路。的BTN8960TA可以与其它BTN8960TA结合，以形成H桥和3-
相驱动配置。-The BTN8960TA is part of the NovalithIC™ family containing three separate chips in one package: One p-channel
highside MOSFET and one n-channel lowside MOSFET together with a driver IC, forming an integrated high
current half-bridge. All three chips are mounted on one common lead frame, using the chip on chip and chip by
chip technology. The power switches utilize vertical MOS technologies to ensure optimum on state resistance.
Due to the p-channel highside switch the need for a charge pump is eliminated thus minimizing EMI. Interfacing
to a microcontroller is made easy by the integrated driver IC which features logic level inputs, diagnosis with
current sense, slew rate adjustment, dead time generation and protection against overtemperature, undervoltage,
overcurrent and short circuit. The BTN8960TA can be combined with other BTN8960TA to form H-bridge and 3-
phase drive configurations.
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Size: 1644544 |
Author: 胜客 |
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Description: This paper discusses the impact of using 3-phase and multipules converter circuit commonly found in unity power factor at
input AC mains and regulates output voltage.3-phase thyristor rectifiers have been used in industries for obtaining a variable DC
voltage, but they have a problem of including large lower-order harmonics in the input currents. For high-power applications, a 12-
pulse, 18-pulse and 24-pulse configuration is useful for reducing the harmonics, but it still includes the (np±1) th (n: integer, p: pulse)
harmonics. In this paper present the rectifiers are using the MATLAB/SIMULINK simulation model and several common conditions
will be simulated to compare their harmonic levels.
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Size: 837632 |
Author: Ashok |
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Description: 三相光伏并网逆变器DSP程序，包括MPPT PLL PID SPWM-3 phase solar inverter DSP，including MPPT PLL PID SPWM
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Size: 4096 |
Author: mzz |
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Description: 演示使用的power_3phsignaldq离散三相位可编程源代码块生成1 p.u.，正序电压15度。在0.05秒的正序电压增加到1.5 p.u.，在0.1秒的不平衡是由一个0.3 p.u.负序分量相位与30度的引入。正序分量的大小和相位用两种不同的方式进行评估(The power_3phsignaldq demo uses a Discrete Three-Phase Programmable Source block to generate a 1 p.u., 15 degrees positive sequence voltage. At 0.05 second the positive sequence voltage is increased to 1.5 p.u. and at 0.1 second an imbalance is introduced by the addition of a 0.3 p.u. negative sequence component with a phase of -30 degrees. The magnitude and phase of the positive-sequence component are evaluated in two different ways:)
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Size: 8192 |
Author: apduaa
|
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Description: 典型测试系统3
(1) 如下图所示的IEEE 9节点电力系统：
2．元件参数
（1） 线路参数
线路号 长度（km） ro(Ω/km) xo(Ω/km) bo(1/Ωkm)
L1 25 0.131 0.4 2.98×10-6
L2 50 0.131 0.4 2.98×10-6
L3 45 0.105 0.393 3.04×10-6
L4 30 0.131 0.4 2.98×10-6
L5 35 0.105 0.393 3.04×10-6
L6 20 0.131 0.4 2.98×10-6
（2） 变压器参数
变压器 容量（MVA） 变比 Pk(kW) P0(kW) Uk% i0%
T1 50 121/10.5 250 55 10.5 1.5
T2 80 121/10.5 410 98 10.5 1.5
T3 50 121/10.5 250 55 10.5 1.5
(3) 节点参数
节点名 类 型 P (MW) Q (MVar) 电压 相角
1 PQ 35 18
2 PQ 30 16
3 PQ 40 20
4 PQ 25 12
5 PQ 20 10
6 PQ 15 6
7 PV 40 1.05
8 PV 45 1.05
9 平衡点 1.05 0.0(Typical test system 3
(1) The IEEE 9-node power system shown in the following figure:
2. Component parameters
(1) Line parameters
Line number (km) ro (_/km) XO (_/km) Bo (1/_km)
L1 25 0.131 0.4 2.98 x 10-6
L2 50 0.131 0.4 2.98 x 10-6
L3 45 0.105 0.393 3 3.04 x 10-6
L4 30 0.131 0.4 2.98 x 10-6
L5 35 0.105 0.393 3 3.04 x 10-6
L6 20.131 0.4 2.98 x 10-6
(2) Transformer parameters
Transformer Capacity (MVA) Variable Ratio Pk (kW) P 0 (kW) Uk% i0%
T1 50 121/10.5 250 55 10.5 1.5
T2 80 121/10.5 410 98 10.5 1.5
T3 50 121/10.5 250 55 10.5 1.5
(3) Node parameters
Node Name Type P (MW) Q (MVar) Voltage Phase Angle
1 PQ 3518
2 PQ 3016
3 PQ 4020
4 PQ 2512
5 PQ 2010
6 PQ 156
7 PV 40 1.05
8 PV 45 1.05
9 Balance Point 1.05 0.0)
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Size: 19456 |
Author: GKen |
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