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Description: 本文给出了一种以80C31为主控CPU的固定电话短信息终端的设计,从系统软硬件两个方面说明了固定电话短信息终端的设计方法和各个部分的工作原理
-This paper proposes a 80C31 CPU for controlling the fixed telephone short message terminal design, system software and hardware from the two showed that the fixed telephone short message terminal design methods and various parts of the work principle
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Size: 240789 |
Author: 口是心非 |
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Description: 利用80C31单片机串行口实现多个LED显示的一种简单方法.
Platform: |
Size: 69632 |
Author: hehui |
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Description: 本文给出了一种以80C31为主控CPU的固定电话短信息终端的设计,从系统软硬件两个方面说明了固定电话短信息终端的设计方法和各个部分的工作原理
-This paper proposes a 80C31 CPU for controlling the fixed telephone short message terminal design, system software and hardware from the two showed that the fixed telephone short message terminal design methods and various parts of the work principle
Platform: |
Size: 240640 |
Author: 口是心非 |
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Description: 利用80C31单片机串行口实现多个LED显示的一种简单方法.-80C31 single-chip serial port to use multiple LED shows a simple method.
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Size: 69632 |
Author: hehui |
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Description: 80c31和0805及dac8032芯片的控制输入输出程序,很好很强大-80c31 and 0805 and dac8032 chip input and output control program, a very powerful
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Size: 5120 |
Author: ssf |
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Description: The 80C31/80C51 is a high-performance microcontroller fabricated with high-density
CMOS technology.
The 80C51 contains a 4k x 8 ROM , a 128 x 8 RAM , 32 I/O lines, two 16-bit
counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port
for either multi-processor communications, I/O expansion or full duplex UART, and onchip
oscillator and clock circuits.
The device has two software selectable modes of power reduction idle mode and
power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial
port, and interrupt system to continue functioning. The power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip functions to be inoperative.-The 80C31/80C51 is a high-performance microcontroller fabricated with high-density
CMOS technology.
The 80C51 contains a 4k x 8 ROM , a 128 x 8 RAM , 32 I/O lines, two 16-bit
counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port
for either multi-processor communications, I/O expansion or full duplex UART, and onchip
oscillator and clock circuits.
The device has two software selectable modes of power reduction idle mode and
power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial
port, and interrupt system to continue functioning. The power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip functions to be inoperative.
Platform: |
Size: 114688 |
Author: Andrew85 |
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