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Description: 1.5-b/s Pipelined A/D behavior model
以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model
Include SNR INL DNL test progrems
Platform: |
Size: 4096 |
Author: jason |
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Description: Simulation of direct digital synthesis sine wave in the MathCAD (10 bit ADC, 16-bit accumulator, 12-bit ROM, the clock frequency of 25MHz)
Platform: |
Size: 13312 |
Author: user |
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