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Description: 一篇简单易懂的关于数字锁相环概念原理设计的经典文章
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Size: 249213 |
Author: 林晓叶 |
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Description: 数字锁相环实现源码，有很大的参考价值。
由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.
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Size: 2482 |
Author: sharny |
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Description: 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。
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Size: 432317 |
Author: 萝卜 |
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Description: 一篇简单易懂的关于数字锁相环概念原理设计的经典文章-An easy-to-read digital phase-locked loop on the concept of the classic principles of design article
Platform: |
Size: 248832 |
Author: 林晓叶 |
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Description: 数字锁相环实现源码，有很大的参考价值。
由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and subtraction to establish surveillance mode N divider circuit constituted.
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Size: 2048 |
Author: sharny |
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Description: 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。
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Size: 432128 |
Author: 萝卜 |
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Description: Digital Vlsi Design With Verilog A Textbook From Silicon Valley Technical Institute.pdf
Thisbookisbasedonthelabexercisesandorderofpresentationofacourse
developedandgivenbytheauthoroveraperiodofyearsatSiliconValleyTech-
nicalInstitute,SanJose,California.
Atthetime,totheauthor°Psbestknowledge,thiscoursewastheonlyoneeve
givenwhich(a)presentedtheentireveriloglanguage (b)involvedimplementation
ofafull-duplexserdessimulationmodel or(c)includeddesignofasynthesizable
digitalPLL.
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Size: 3462144 |
Author: Frank |
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