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Description: C8051F单片机是完全集成的混合信号系统级芯片（SoC），具有与8051兼容的高速CIP-51内核，与MCS-51指令集完全兼容，片内集成了数据采集和控制系统中常用的模拟、数字外设及其他功能部件；内置FLASH程序存储器、内部RAM，大部分器件内部还有位于外部数据存储器空间的RAM，即XRAM。C8051F单片机具有片内调试电路，通过4脚的JTAG接口可以进行非侵入式、全速的在系统调试。-C8051F is a fully integrated mixed-signal system-on-chip (SoC), and 8051 compatible with the high-speed CIP-51 core, and MCS-51 compatible instruction set, on-chip integration of the data acquisition and control system used in analog and digital peripherals, and other functional components; embedded Flash program memory, internal RAM, the majority of devices located within the external data memory space of RAM, XRAM. C8051F with on-chip debug circuit, through the four legs of the JTAG interface can be non-invasive, full-speed debugging of the system.
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Size: 29748 |
Author: 覃莉 |
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Description: C8051F单片机是完全集成的混合信号系统级芯片（SoC），具有与8051兼容的高速CIP-51内核，与MCS-51指令集完全兼容，片内集成了数据采集和控制系统中常用的模拟、数字外设及其他功能部件；内置FLASH程序存储器、内部RAM，大部分器件内部还有位于外部数据存储器空间的RAM，即XRAM。C8051F单片机具有片内调试电路，通过4脚的JTAG接口可以进行非侵入式、全速的在系统调试。-C8051F is a fully integrated mixed-signal system-on-chip (SoC), and 8051 compatible with the high-speed CIP-51 core, and MCS-51 compatible instruction set, on-chip integration of the data acquisition and control system used in analog and digital peripherals, and other functional components; embedded Flash program memory, internal RAM, the majority of devices located within the external data memory space of RAM, XRAM. C8051F with on-chip debug circuit, through the four legs of the JTAG interface can be non-invasive, full-speed debugging of the system.
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Size: 29696 |
Author: 覃莉 |
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Description: 本书介绍了Cygnal集成产品公司(C8051Fxxx高速片上系统(SOC)单片机的硬件结构和工作
原理，详细阐述了C8051Fxxx的定时器、可编程计数器阵列(PCA)、串行口、SMBus/IIC接口、SPI总线接口、ADC、DAC、比较器、复位源、振荡器、看门狗定时器、JTAG接口等外设或功能部件的结构和使用方法。本书还介绍了Cygnal单片机的软件开发环境及典型应用。
-This book introduces Cygnal Integrated Products (C8051Fxxx high-speed system-on-chip (SOC) MCU hardware structure and working principle of the C8051Fxxx detailed timers, programmable counter array (PCA), serial port, SMBus/IIC interface, SPI bus interface, ADC, DAC, comparators, reset the source oscillator, watchdog timer, JTAG interface or peripheral features, such as the structure and use. This book also introduced the single-chip Cygnal software development environment and a typical application.
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Size: 5271552 |
Author: l gd |
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Description: 用于调试openrisc系统的gdb与jtag桥程序
相当于驱动程序，内包含说明文档，很详细-driver of gdb and jtag, use for openrisc embeded soc system debug
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Size: 405504 |
Author: renwei |
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Description: 晓舟通用在线调试系统(MornShip Universal Online Debug System，简称MSUODS)是晓舟工作室研发的具有完全自主知识产权的通用型嵌入式实时在线调试系统。MSUODS针对所有采用8051(兼容)指令的芯片，利用串口通讯实现了通行在线调试仿真系统(ICE/JTAG)的所有在线调试仿真功能，具有性价比高，资源消耗少，不受芯片型号限制的通用性，支持多种类型和数量不受限制的断点设置，基于多种集成开发环境(IDE)的源码级在线调试，支持二次开发等众多特点-MornShip Universal Online Debug System (MSUODS), for all 8051 (compatible) instructions MCU/DSP/SoC chip, via the UART interrupt communication, implement all function of the general online debug & simulator system. The feature of MSUODS include high performance/price ratio, less resources consumption, universal to all type of chip, support multi-type and no-limited breakpoints, source code level online debug base on multi Integrated Development Environment(IDE), support secondary development and so on
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Size: 530432 |
Author: xuezhen |
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Description: 本文首先介绍了JTAG标准和SoC调试技术，研究了基于JTAG的多核SoC调试结构，优化了一种全兼容多核SoC调试结构，使JTAG控制器的互连能配置成多种模式，以实现单核或多核SoC调试；然后在IEEEl 149．1标准的基础上进行了结构化改进，扩展了指令集与寄存器，实现了基于JTAG标准的SoC调试系统；最后进行了SoC调试系统的功能测试与性能分析，测试结果表明本文实现的SoC调试系统比现有的同类调试工具在功能与性能方面都有明显提高。-This paper describes the JTAG standard and SoC debugging technology, research-based JTAG debugging multi-core SoC structure, optimized multi-core SoC debugging a fully compliant structure, the JTAG controller can be configured into a variety of interconnect models in order to achieve a single-core or multi-core SoC debugging then IEEEl 149.1 standard structured on the basis of improved, expanded instruction set and registers, to achieve standards-based SoC JTAG debug system Finally, a functional test system SoC debugging and performance analysis The test results show that the implementation of SoC debug system debugging tools than the existing similar in function and performance are improved obviously.
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Size: 2661376 |
Author: 李立 |
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Description: Recovery tool for BCM6348 based DSL routers. This SoC have a bizzare bug, that prevents entering CPU debug mode via jtag, if ADSL controller inside BCM is not initialized (if you compile the original firmware without DSL driver, you are also not be able to enter debug). This tool completly bypass CPU, and access flash via jtag boundary scan,so you may flash CFE directly on board. But for this, you must put out 64Mhz crystall to stop CPU core before. I tested this tool on DSL-2640RU Rev B2 router, but with MX29LV160 flash. I have nt native 32Mbit flash.
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Size: 147456 |
Author: 0xB0BA |
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Description: On-Chip Instrumentation_Design and Debug for Systems on Chip--Neal Stollon.pdf
本书介绍了对于SOC调试系统的设计，包括jtag、jtag、etm等内容。整书对emulator和tracer的介绍非常详细。-This book give a detail description for design a debugging system on SoC system.
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Size: 6659072 |
Author: kyle |
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Description: SOC程序设计指南与FPGA jatg使用开发指南与技术指导手册，适用于初学者学习和使用。-Design guidelines and the FPGA jatg use SOC program development guide and technical guide, suitable for beginners to learn and use.
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Size: 333824 |
Author: KO |
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Description: Xilinx虚拟连接，这是一种基于TCP/IP协议的通信技术，以实现JTAG功能，通过这样的连接，可以访问开发的FPGA或者SOC，而不需要通过传统的JTAG电缆。(Xilinx Virtual Cable (XVC) is a TCP/IP-based communication protocol that acts
like a JTAG cable and provides a means to access and debug your FPGA or SoC
design without using a physical cable. In this document are the general details
of this XVC 1.0 protocol.)
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Size: 8192 |
Author: forestmeng
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