Description: 电力系统在台稳定计算式电力系统不正常运行方式的一种计算。它的任务是已知电力系统某一正常运行状态和受到某种扰动，计算电力系统所有发电机能否同步运行
1运行说明：
请输入初始功率S0，形如a+bi
请输入无限大系统母线电压V0
请输入系统等值电抗矩阵B
矩阵B有以下元素组成的行矩阵
1正常运行时的系统直轴等值电抗Xd
2故障运行时的系统直轴等值电抗X d
3故障切除后的系统直轴等值电抗
请输入惯性时间常数Tj
请输入时段数N
请输入哪个时段发生故障Ni
请输入每时段间隔的时间dt-power system stability in the Taiwan Power computing system is not the normal operating mode of calculation. Its mission is a known power system uptime status and be subject to some disturbance, computing power system all synchronous generator can run an operation Note : Please enter the initial power S0, shaped like a bi Please enter the infinite system bus voltage V0 Please enter the system equivalent reactance matrix B matrix B group has the following elements the line matrix into a normal operation of the system straight axis equivalent reactance Xd two fault systems running straight axis equivalent reactance X d 3 after resection of the fault system straight axis equivalent reactance Please enter the inertial time constant Tj Please enter the number of hours which N Please enter a tim Platform: |
Size: 1107 |
Author:魏鹏 |
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Description: 这篇实验报告是关于单片机多路数据采集的，本实验由2大部分组成：1、为用EPOROM构成的心电信号发生器；2、为多路信号的微机采集与显示；第一部分实验主要研究可编程序存储器EPROM的非计算机应用。把存储在EPROM中的数字心电信号读出并通过D/A转换为模拟信号显示在示波器屏幕上。
第二部分实验的目的是研究一个数据采集系统，该系统利用ECD-51型单片机为中心，由D/A芯片等将各种低频信号以及由EPROM产生的模拟人体心电信号变换成离散的数字信号存入微机内存，以待进行数据处理和分析，然后再通过D/A转换将其还原成模拟信号显示在示波器的屏幕上。
-This experimental report on the multi-SCM data acquisition, the experiment by the two major components : 1. EPOROM pose for the use of the ECG signal generator; 2, multi-path signals in the computer acquisition and display; the first major study of experimental programmable EPROM memory in non-computer applications. Stored in the EPROM of ECG read out by D / A conversion of analog signals displayed on the oscilloscope screen on. Part II The purpose of this experiment is to study a data acquisition system, which uses ECD-51 microprocessor as the center, from the D / A chips, and other various low-frequency signal from EPROM and the simulation of human ECG transform into several discrete signal words into computer memory, pending data processing and analysis, then through D / A conversion re Platform: |
Size: 75321 |
Author:蔡育瑜 |
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Description: 电力系统在台稳定计算式电力系统不正常运行方式的一种计算。它的任务是已知电力系统某一正常运行状态和受到某种扰动，计算电力系统所有发电机能否同步运行
1运行说明：
请输入初始功率S0，形如a+bi
请输入无限大系统母线电压V0
请输入系统等值电抗矩阵B
矩阵B有以下元素组成的行矩阵
1正常运行时的系统直轴等值电抗Xd
2故障运行时的系统直轴等值电抗X d
3故障切除后的系统直轴等值电抗
请输入惯性时间常数Tj
请输入时段数N
请输入哪个时段发生故障Ni
请输入每时段间隔的时间dt-power system stability in the Taiwan Power computing system is not the normal operating mode of calculation. Its mission is a known power system uptime status and be subject to some disturbance, computing power system all synchronous generator can run an operation Note : Please enter the initial power S0, shaped like a bi Please enter the infinite system bus voltage V0 Please enter the system equivalent reactance matrix B matrix B group has the following elements the line matrix into a normal operation of the system straight axis equivalent reactance Xd two fault systems running straight axis equivalent reactance X d 3 after resection of the fault system straight axis equivalent reactance Please enter the inertial time constant Tj Please enter the number of hours which N Please enter a tim Platform: |
Size: 1024 |
Author:魏鹏 |
Hits:
Description: 这篇实验报告是关于单片机多路数据采集的，本实验由2大部分组成：1、为用EPOROM构成的心电信号发生器；2、为多路信号的微机采集与显示；第一部分实验主要研究可编程序存储器EPROM的非计算机应用。把存储在EPROM中的数字心电信号读出并通过D/A转换为模拟信号显示在示波器屏幕上。
第二部分实验的目的是研究一个数据采集系统，该系统利用ECD-51型单片机为中心，由D/A芯片等将各种低频信号以及由EPROM产生的模拟人体心电信号变换成离散的数字信号存入微机内存，以待进行数据处理和分析，然后再通过D/A转换将其还原成模拟信号显示在示波器的屏幕上。
-This experimental report on the multi-SCM data acquisition, the experiment by the two major components : 1. EPOROM pose for the use of the ECG signal generator; 2, multi-path signals in the computer acquisition and display; the first major study of experimental programmable EPROM memory in non-computer applications. Stored in the EPROM of ECG read out by D/A conversion of analog signals displayed on the oscilloscope screen on. Part II The purpose of this experiment is to study a data acquisition system, which uses ECD-51 microprocessor as the center, from the D/A chips, and other various low-frequency signal from EPROM and the simulation of human ECG transform into several discrete signal words into computer memory, pending data processing and analysis, then through D/A conversion re Platform: |
Size: 74752 |
Author:蔡育瑜 |
Hits:
Description: E=input( enter the generator voltage: )
V=input( enter the infinite bus voltage: )
Gx=input( enter the reactance of generator: )
L1x=input( enter the line reactance: )
L2x=input( enter the line reactance: )
L3x=input( enter the line reactance: )
L4x=input( enter the line reactance: )
Pi=input( enter the input power: )
X1=Gx+L1x+((L2x*L3x)/(L2x+L3x))+L4x
Pm1=E*V/X1
DO=asin(Pi/Pm1)
A=((L2x*L3x)/(2*(L2x+L3x)))
C=A
B=((L3x/2)^2)/(L2x+L3x)
X2=(Gx+L1x+A)+(L4x+A)+(Gx+L1x+A)*(A+L4x)/B
Pm2=(E*V)/X2
X3=Gx+L1x+L2x+L4x
Pm3=(E*V)/X3
DC=input( enter the fault clearing angle: )
Dm=(3.14-asin(Pi/Pm3))
a1=quad( sin ,DO,DC)
A1=(Pi*(DC-DO)-Pm2*a1)
a2=quad( sin ,DC,Dm)
A2=Pm3*a2-Pi*(Dm-DC)
if(A2>=A1)
disp( the system is stable )
else
disp( the system is unstable )
end
Dcc=acos((Pi*(Dm-DO)-Pm2*(cos(DO))+Pm3*(cos(Dm)))/(Pm3-Pm2))
disp( critical clearing angle: )
D-E=input( enter the generator voltage: )
V=input( enter the infinite bus voltage: )
Gx=input( enter the reactance of generator: )
L1x=input( enter the line reactance: )
L2x=input( enter the line reactance: )
L3x=input( enter the line reactance: )
L4x=input( enter the line reactance: )
Pi=input( enter the input power: )
X1=Gx+L1x+((L2x*L3x)/(L2x+L3x))+L4x
Pm1=E*V/X1
DO=asin(Pi/Pm1)
A=((L2x*L3x)/(2*(L2x+L3x)))
C=A
B=((L3x/2)^2)/(L2x+L3x)
X2=(Gx+L1x+A)+(L4x+A)+(Gx+L1x+A)*(A+L4x)/B
Pm2=(E*V)/X2
X3=Gx+L1x+L2x+L4x
Pm3=(E*V)/X3
DC=input( enter the fault clearing angle: )
Dm=(3.14-asin(Pi/Pm3))
a1=quad( sin ,DO,DC)
A1=(Pi*(DC-DO)-Pm2*a1)
a2=quad( sin ,DC,Dm)
A2=Pm3*a2-Pi*(Dm-DC)
if(A2>=A1)
disp( the system is stable )
else
disp( the system is unstable )
end
Dcc=acos((Pi*(Dm-DO)-Pm2*(cos(DO))+Pm3*(cos(Dm)))/(Pm3-Pm2))
disp( critical clearing angle: )
Dcc Platform: |
Size: 7168 |
Author:tkspandy |
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Description: 数字系统CAD 开发平台实验部分共有6 个实验，内容覆盖了ISE 的设计使用、片内逻
辑分析仪ChipScope 的使用、设计仿真工具Modelsim 的使用、以及嵌入式系统设计工具EDK的使用等内容。在每个实验的说明中分别介绍它们的使用。
包括：
实验一、7 段数码管显示简单的时钟
实验二、设计串口与计算机通信
实验三、A/D 采样模块设计
实验四、使用DAC7634 设计频率发生器
实验五、频率发生器的设计与仿真
实验六、应用嵌入式系统设计基本的串口收发程序
实验七、视频解码和图像显示-CAD development platform for digital system experimental part of a total of six experiments, the content covers the use of ISE design, on-chip logic analyzer ChipScope use, the design of the use of ModelSim simulation tools, as well as embedded system design tools such as content use EDK. In each experiment, respectively, a note on their use. Include: the experimental one, paragraph 7 of digital display clock simple experiment II, the design of serial communication and computer experiment III, A/D sampling experiment four modular design, the use of design DAC7634 experimental five-frequency generator, frequency generator design and simulation Experimental six, application of embedded system design basic experimental procedures seven serial transceiver and video decoding and image display Platform: |
Size: 1178624 |
Author:abcoabco |
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Description: 现代电子系统课程设计
基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。
（1）基本要求：
a．频率范围：1Hz～4kHz，频率步进为1Hz，输出频率可预置。
b．A、B两路正弦信号输出，10位输出数据宽度
c．相位差范围为0～359°，步进为1.4°，相位差值可预置。
d．数字显示预置的频率（10进制）、相位差值。
（2）发挥部分
a．修改设计，增加幅度控制电路（如可以用一乘法器控制输出幅度）。
b．输出幅度峰峰值0.1～3.0V，步距0.1V，显示预置值。
-Modern electronic system design is based on DDS technology courses use VHDL to design and produce a digital shift Signal Generator. (1) the basic requirements: a. Frequency range: 1Hz ~ 4kHz, frequency step for the 1Hz, output frequency can be preset. b. A, B two sinusoidal signal output, 10-bit output data width c. Phase difference range of 0 ~ 359 °, stepping to 1.4 °, the phase difference value can be preset. d. Figures show that the frequency of Preferences (10 M), phase difference value. (2) to play a part of a. Modify the design to increase the rate of control circuit (for example, could use a multiplier to control the output rate). b. Peak-to-peak output rate of 0.1 ~ 3.0V, step 0.1V, show preset value. Platform: |
Size: 174080 |
Author:耳边 |
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Description: 根据TLC7524输出控制时序，利用接口电路图，通过改变输出数据，设计一个正弦波发生器。TLC7524是8位的D/A转换器，转换周期为 ，所以锯齿波型数据有256个点构成，每个点的数据长度为8位。.FPGA的系统时钟为 ，通过对其进行5分频处理，得到频率为 的正弦波-TLC7524 output under the control of timing, the use of interface circuit, by changing the output data, the design of a sine wave generator. TLC7524 8-bit D/A converter, the conversion cycle, so sawtooth 256 data points, each point of the data length of 8. . FPGA system clock as, through its 5-band processing, the frequency of the sine wave Platform: |
Size: 1024 |
Author:离火 |
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Description: 基于软件无线电的SFF平台，采用Xilinx System Generator实现的数字上变频器-SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter Platform: |
Size: 53248 |
Author:刘荣毅 |
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Description: 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时，显示满刻度为23时59分59秒，并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源，采用低功耗的芯片及液晶显示器，发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74，计数器采用同步双十进制计数器74LS160，锁存译码器是74LS248，整电报时电路用74LS74，74LS32及扬声器构成。-Design a digital circuit, on the hours, minutes, seconds. Figures show that the timing device, 24-hour period, indicating full scale is 23:59:59 and the time with school functions and timekeeping functions of digital electronic clock. Scale integrated circuits used in the main circuit. The design of this system by the pulse logic circuit module, clock module, the clock display circuit decoding module, when the entire cable module, the campus module components. Using a battery powered, low-power chips and liquid crystal display generator using a quartz crystal oscillator, count of CD4060 oscillator and two D flip-flop 74LS74, two-decimal counter synchronous counter 74LS160, latch decoder is the 74LS248, the whole When telegraph circuits 74LS74, 74LS32 and loudspeaker Platform: |
Size: 449536 |
Author:张龙 |
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Description: 信号发生器是一种常用的信号源，广泛地应用于电子电路、自动控制系统和教学实验等领域。目前使用的信号发生器大部分是函数信号发生器，且特殊波形发生器的价格昂贵。所以本设计使用的是AT89c51单片机构成的发生器，可产生三角波、方波、正弦波等多种特殊波形和任意波形，波形的频率可用程序控制改变。在单片机上加外围器件距阵式键盘，通过键盘控制波形频率的增减以及波形的选择，并用了LCD显示频率大小。在单片机的输出端口接DAC0832进行D/A转换，再通过运放进行波形调整，最后输出波形接在示波器上显示。本设计具有线路简单、结构紧凑、价格低廉、性能优越等优点。- Signal-generator is a kind of signal source in common use, broadly applied at the electronics electric circuit, auto control system and teaching experiment etc. Currently used mostly function signal generator signal generator, waveform generator and a special price of expensive . So the dissertation is usage of the AT89s51 single-chip microcomputer constitute of wave-form generator, which can generate triangle wave, square wave, sine wave etc variety wave-form, the period of wave can be controlled by procedure, at outer circle spare part of the machine, plus independence type keyboard , which can control wave increase or decrease of form-frequency and the choice of wave-form, at the same time LED display frequency size. The output of the machine connect DAC0832 to carry on a DA conversion，again pass operation amplifier to put an end exportation wave-form. This design has advantage of simple circuit, tightly packed structure, cheap price, superior function etc. Platform: |
Size: 2048 |
Author: |
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Description: 该高频正弦信号发生器基于直接数字频率合成（DDS）和数字锁相环技术（DPLL），以微控制器（MCU）和现场可编程逻辑门阵列（FPGA）为核心，辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数（A/D）－数模（D/A）转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a microcontroller (MCU) and field programmable gate array (FPGA) as the core, supplemented by the necessary peripheral from circuit design. System is composed of sinusoidal signal, infrared remote control, high-speed module (A/D)- digital-analog (D/A) conversion, signal modulation and post-level processing modules. Platform: |
Size: 243712 |
Author:henry |
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Description: 本次仿真研究多幅度电平信号误码率与信噪比之间的关系，系统框图如上。假设考虑8幅度电平，则根据流程首先需要用一个随机数发生器产生在(0,1)间的均匀随机数，然后将(0,1)区间均匀划分为(0,0.125)、(0.125,0.25)、(0.25,0.375)、(0.375,0.5)、(0.5,0.625)、(0.625,0.75)、(0.75,0.875)、(0.875,1)这些子区间，并分别对应于一个3bit符号000、001、010、011、100、101、110、111，接着分别映射到-7d、-5d、-3d、-d、d、3d、5d、7d幅度电平上。之后高斯随机数与幅度电平叠加(高斯噪声的方差由输入信噪比控制)，生成随机幅度r。通过与判定门限的比较判定r的符号值，然后与输入符号比较，如果不等则认为此符号传送错误。本实验假定进行10000次信号发送，计算发送错误的比例作为仿真误码率。
另外计算对应不同信噪比情况下理论误码率的值，与上述实验进行对比验证。
-The simulation of multi-amplitude level signal bit error rate and the relationship between SNR, the system block diagram above. Assumption consider the magnitude of level 8, then according to the process you first need to use a random number generator in (0,1) uniform random number, then (0,1) interval is divided into uniform (0,0.125), (0.125 , 0.25), (0.25,0.375), (0.375,0.5), (0.5,0.625), (0.625,0.75), (0.75,0.875), (0.875,1) These sub-intervals, and corresponding to a symbol 3bit 000,001,010,011,100,101,110,111, and then are mapped to-7d,-5d,-3d,-d, d, 3d, 5d, 7d on the amplitude level. After the Gaussian random number with the amplitude level overlay (Gaussian noise of variance controlled by the input signal to noise ratio) to generate a random rate r. By comparison with the determined threshold value to determine the sign of r, and then compared with the input symbol, if the range is that this symbol transmission error. This study assumes that the signal sent 10000, send an error Platform: |
Size: 2048 |
Author:ps |
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Description: EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。-Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
Platform: |
Size: 33792 |
Author:王丽丽 |
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Description: 用MSP430 launch pad制作一个简易的方波信号发生器，要求：
使用MSP430的Timer_A产生方波信号，方波信号频率范围：1KHz~10KHz
方波信号的频率由外部电压控制，电压范围为0-2V，输入电压和输出频率呈线性关系；
外部电压信号由MSP430的片内A/D采集；
外部输入电压由电位器产生；
输出信号的频率误差<10Hz；
系统上电以后默认输出方波信号1kHz。
增加按键控制功能，当S2（P1.3)按下时，通过改变外部输入电压可控制方波信号频率，当S2（P1.3）松开后，外部输入信号对方波信号输出频率无影响。-The pad produced a simple square wave signal generator, the MSP430 launch requirements: MSP430 Timer_A produce a square wave signal, a square wave signal frequency range: 1KHz ~ 10KHz the frequency of square wave signal is controlled by an external voltage, the voltage range of 0- 2V input voltage and output frequency is a linear relationship external voltage signal from the MSP430 on-chip A/D acquisition external input voltage generated by the potentiometer default output square wave signal in the output signal of the frequency error < 10Hz system power after 1kHz. Increase the key control function of S2 (P1.3) is pressed, by changing the external input voltage square wave signal frequency can be controlled, no effect of S2 (P1.3) release, the square wave signal output frequency of the external input signal. Platform: |
Size: 25600 |
Author:hu |
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Description: 编制一个参数在线可调的波形发生程序，由D／A 输出，构成参数在线可调的波形发生器，并用示波器观察波形。
（1）函数波形可选f(t)=asin(bt)，其中a、ｂ参数在线可调（亦可自己选择，但要求至少2个参数可调且调节很明显）；
（2）参数调节采用如下两种方式之一：两个可调电位器输出通过A／D 转换后作为可调参数、参数通过实验系统上的键盘实时修改
-The preparation of an argument online adjustable waveform generation program, by the D/A output form online waveform generator with adjustable parameters, and observed with an oscilloscope waveform. (1) The function waveform optional f (t) = asin (bt), where a, b adjustable parameters online (also their choice, but requires at least two adjustable parameters and adjustment obviously) (2) adjusting parameters using one of the following two ways: two adjustable potentiometer output by the A/D converter as an adjustable parameter, the parameters through the keyboard on the experimental system real-time modifications Platform: |
Size: 2048 |
Author:张 |
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Description: Hybrid PV-wind generation shows higher
availability as compared to PV or wind alone. For rural
electrifications, researches are focused on hybrid power system
which provides sustainable power. The variable voltage and
frequency of the self excited induction generator (SEIG) is
rectified through Vienna rectifier (three switches) to the required
D.C voltage level and fed to common D.C bus. The variable output
voltage of PV module is controlled by DC/DC converter using
proposed fuzzy logic controller and fed to common D.C bus. The
DC bus collects the total power from the wind and photovoltaic
system and used to charge the battery as well as to supply the A.C
loads through inverter. A dynamic mathematical model and
MATLAB simulations for the entire scheme is presented. Results
from the simulations and experimental tests bring out the
suitability of the proposed hybrid scheme in remote areas. Platform: |
Size: 48128 |
Author:hareesh |
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