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[Other resource] mentor DL : 0: Cadence设计系统公司（纽约证券交易所代码：CDN）和广晟微电子公司今天共同宣布，广晟已经通过Cadence Virtuoso 全定制平台成功地开发出第一代10Gbps高速光传输集成电路（IC），而且只用了不到16个星期的时间。借助Virtuoso全定制设计平台为先进的全定制IC设计提供的整合平台、完整流程以及最优化的技术，广晟无需进行硅反复设计即可制作出复杂的通讯用集成电路。
Update : 2008-10-13 Size : 3.55mb Publisher : 谢峰
[Other resource] Cadence_MEDICI DL : 0: 本手册共分为三部分：第一部分分为四章，分别介绍Cadence cdsSpice、virtuoso Editing、Diva和verilog。第二部分主要介绍MEDICI。第三部分是附录部分，是对前两章的一个补充,并简要的介绍了寄生元件提取语句的语法。
Update : 2008-10-13 Size : 15.97mb Publisher : zjh
[Books] cadence DL : 0: cadence教程。内容全面，各种检证方法详细列举。适合各种层次的学习者。-cadence tutorial. Comprehensive range of inspection methods in detail. Suitable for all levels of learners.
Update : 2025-02-17 Size : 1.6mb Publisher : luo
[Software Engineering] mentor DL : 0: Cadence设计系统公司（纽约证券交易所代码：CDN）和广晟微电子公司今天共同宣布，广晟已经通过Cadence Virtuoso 全定制平台成功地开发出第一代10Gbps高速光传输集成电路（IC），而且只用了不到16个星期的时间。借助Virtuoso全定制设计平台为先进的全定制IC设计提供的整合平台、完整流程以及最优化的技术，广晟无需进行硅反复设计即可制作出复杂的通讯用集成电路。 -Cadence Design Systems, Inc. (NYSE: CDN) and Rising Micro Electronics Corporation today announced that Rising has adopted Cadence Virtuoso Custom Platform successfully developed the first-generation 10Gbps optical transmission of high-speed integrated circuits (IC), and only less than 16 weeks time. With Virtuoso Custom Design Platform for advanced full-custom IC design platform to provide integrated, complete and optimize the flow of technology, widely sung repeatedly the need for the design of silicon can produce complex integrated circuits for communications.
Update : 2025-02-17 Size : 3.55mb Publisher : 谢峰
[Other] Cadence_MEDICI DL : 1: 本手册共分为三部分：第一部分分为四章，分别介绍Cadence cdsSpice、virtuoso Editing、Diva和verilog。第二部分主要介绍MEDICI。第三部分是附录部分，是对前两章的一个补充,并简要的介绍了寄生元件提取语句的语法。-This manual is divided into three parts: the first part is divided into four chapters, respectively, introduce Cadence cdsSpice, virtuoso Editing, Diva and verilog. Introduce the second part of the main MEDICI. The third part is the appendix of the first two chapters of a supplement to, and briefly introduce the components of the parasitic extraction statement grammar.
Update : 2025-02-17 Size : 15.97mb Publisher : zjh
[Other systems] CalculateWL DL : 0: 计算电路中晶体管的关键参数。界面友好，功能实用。-a useful tools to calculate the scale of mos transistor. This Program is dedicated to calculate the Parameters of the MOSFET in analog IC design. Microsoft .net framework 2.0 or above is needed. 1) Input every THREE parameters in (Ids, Vdsat, Vds, W/L) to claculate the other one. Leave the textbox of the parameter to be calculated in EMPTY. 2) Input the ABS value of Ids, Vdsat and Vds for pmos. 3) Fast Switch: Use space, enter or tab to switch to the next input area quickly. 4) Dynamic Increase: Press the button "+" to increase the number of MOSFET. 5) Program can minizied to system tray. Click to bring it to front. 6) Select "On Top" when you finished calculation and intput data in other programs like Cadence Virtuoso.
Update : 2025-02-17 Size : 14kb Publisher : 杜睿
[Windows Develop] 93317460Cadence_HandBOOK DL : 0: virtuoso软件非常好大家看看，如果需要就可以下了是一些virtuoso的中文资料很难得啊 -virtuoso
Update : 2025-02-17 Size : 1.45mb Publisher : 唐志晨
[Other] Virtuoso-XL_Layout_Editor DL : 0: Virtuoso-XL_Layout_Editor best free cadence tutorial material guide in design asic and soc
Update : 2025-02-17 Size : 2.79mb Publisher : loktikvj
[Other] bus DL : 0: 在cadence virtuoso 下画bus的skill程序。-In the cadence virtuoso painting under the bus of the skill procedure.
Update : 2025-02-17 Size : 1kb Publisher : cgqiao
[Other] alignObj DL : 0: 在cadence virtuoso 下自动对齐已选中的layout-In the cadence virtuoso, automatic alignment has been selected layout
Update : 2025-02-17 Size : 4kb Publisher : cgqiao
[Other] chlib DL : 1: 在cadence virtuoso schematic 自动替换已有的cell到不同的lib-In the cadence virtuoso schematic automatically replace the existing cell to a different lib
Update : 2025-02-17 Size : 7kb Publisher : cgqiao
[Other] spHiCreateMultiLabel DL : 0: 在cadence virtuoso layout下可以自动/手动打label-In the cadence virtuoso layout may be automatic/manual beat label
Update : 2025-02-17 Size : 2kb Publisher : cgqiao
[Other] Tap_MPP DL : 0: 在cadence virtuoso layout下画tap的程序-In the cadence virtuoso layout program under the painted tap
Update : 2025-02-17 Size : 4kb Publisher : cgqiao
[Linux-Unix] BinKeys DL : 0: layout时有西功能没有快捷键，以下脚本就增加一些好用的功能的快捷方式，可更改。-add Cadence virtuoso ShortKey
Update : 2025-02-17 Size : 1kb Publisher : chenyugu
[Other] deletevia DL : 0: 删除孤立过孔，cadence skill开发的程序-delete via
Update : 2025-02-17 Size : 2kb Publisher : oday
[Linux-Unix] Virtuoso_Analog_Design_Environment DL : 0: 通过一些基本操作熟悉Linux 操作系统下Virtuoso Analog Design Environment 设计工具。 Virtuoso Analog Design Environment 是一个在Design Framework II 设计软件系列中的一个，它可以进行输出波形查看，模拟仿真等，Virtuoso Analog Design Environment 有一个非常友好的图形界面。-Familiar with some basic operations through the Linux operating system Virtuoso Analog Design Environment design tool. Virtuoso Analog Design Environment is a design in the Design Framework II software in a series, it can be output waveform view, simulation, etc., Virtuoso Analog Design Environment has a very friendly graphical interface.
Update : 2025-02-17 Size : 2.04mb Publisher : 史培霖
[SCM] New-Folder DL : 0: Cadence User Manual contents: Introduction to Cadence. Basic Features Schematic Edition and Circuit Simulation with Cadence DFWII and Spectre / Hspice,Affirma Schematic Edition and Simulation of an OTA Layout Edition and Verification using Virtuoso
Update : 2025-02-17 Size : 7.07mb Publisher : Priyanka G
[Other] Virtuoso-Schematic-Editor-SKILL-Fun DL : 0: Virtuoso Schematic Editor SKILL Fun
Update : 2025-02-17 Size : 18.98mb Publisher : 段倩妮
[Other] Virtuoso-Preview-SKILL-Functions-Re DL : 0: Virtuoso Preview SKILL Functions Re
Update : 2025-02-17 Size : 19.56mb Publisher : 段倩妮
[Other] CreateBus DL : 0: virtuoso中创建bus线的skill程序(Skill program for creating bus line in virtuoso)
Update : 2025-02-17 Size : 2kb Publisher : nihao040

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