Description: 论文针对数字通信系统中，由于码间串扰(ISI)和信道加性噪声的干扰，导致信号在接收端产生误码，设计了基于LMS算法的自适应均衡器(滤波器)，并通过硬件描述语言VHDL和现场可编程逻辑器件FPGA实现均衡器的硬件实现。是一篇标准的毕业论文,有需要的朋友可以拿来做参考-Thesis for digital communications systems, crosstalk due to inter-symbol (ISI) and additive noise channel interference, leading to signals generated in the receiver error, design algorithm based on LMS adaptive equalizer (filter), and through hardware description languages VHDL and Field Programmable Logic Device FPGA hardware equalizer realize realize. Is a standard thesis, there is a need to make friends can be used as reference Platform: |
Size: 2353152 |
Author:YZ |
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Description: 描述了一个用于微波传输设备的16QAM接收机解调芯片的FPGA实现,芯片集成了定时恢复、载波恢复和自适应盲判决反馈均衡器(DFE),采用恒模算法(CMA)作为均衡算法。芯片支持高达25M波特的符号速率,在一片EP1C12Q240C8(ALTERA)上实现,即将用于量产的微波传输设备中。
-Describes a microwave transmission equipment for 16QAM receiver demodulator chip FPGA realization of an integrated chip timing recovery, carrier recovery and blind adaptive decision feedback equalizer (DFE), using constant modulus algorithm (CMA) as the equalization algorithm. Chip supports up to 25M baud symbol rate, in the midst of EP1C12Q240C8 (ALTERA) achieved for the upcoming production of microwave transmission equipment. Platform: |
Size: 281600 |
Author:萝卜 |
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Description: 是二阶RLS自适应均衡的实现，采用V—LOG编写而成，是从工程中截取的
可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly Platform: |
Size: 5120 |
Author:刘伟 |
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