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Description: 模拟内存高速缓存技术C源码，主要是FIFO形式。-simulated high-speed cache memory technology C source code, is the main form of FIFO.
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Size: 2048 |
Author: 夏军 |
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Description: The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
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Size: 299008 |
Author: sandeep |
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Description: This is paper on post silicon verification of cache coherence.
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Size: 211968 |
Author: Udit |
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Description: The MESI protocol (known also as Illinois protocol due to its development at the University of Illinois at Urbana-Champaign) is a widely used cache coherency and memory coherence protocol. It is the most common protocol which supports write-back cache. Its use in personal computers became widespread with the introduction of Intel s Pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"[1].
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Size: 17408 |
Author: Peetar Parker |
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Description: Handle issues around the Tile "home cache" model of coherence for Linux.
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Size: 5120 |
Author: yiepuitei |
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Description: ：SoC技术的发展使多个异构的处理器集成到一个芯片成为可能．这种结构已成为提高微处理器性能的重要途径。与
传统的多处理器系统一样．Cache一致性问题也是片内异构多处理器系统必须首先解决的问题。本文在分析Cache一致性问
题的基础上．对采用不同监听协议的多处理器的集成．以牺牲简单的硬件为代价来完成一致性协议的转化。将此方法并入
多处理器芯片封装内来管理．可保证在异构多处理器系统中数据的一致性-The development of SoC technology make many heterogeneous processor integrated go to a chip become possibility．This
structure has become an important way to improve performance of microprocessors．An important issue in integrating multiple heteroge·
neous processors on the same chip is to maintain the coherence of their data caches．In this paper，we discuss the cache coherence，
with the sacrificing of simple hardware to completed the transformation of coherence protocol for adopting different snoopy protoc01．
The method can be incorporated in the wrapper to manage the data coherence among heterogeneous processors．
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Size: 364544 |
Author: zh |
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Description: As Internet and information technology have continued developing, the necessity for fast packet processing in computer networks has also grown in importance. All emerging network applications require deep packet classification as well as security-related processing and they should be run at line rates. Hence, network speed and the complexity of network applications will continue increasing and future network processors should simultaneously meet two requirements: high performance and high programmability. We will show that the performance of single processors will not be sufficient to support future demands. Instead, we will have to turn to multicore processors, which can exploit the parallelism in network workloads. In this paper, we focus on the cache coherence protocols which are central to the design of multicore-based network processors. We investigate the effects of two main categories of various cache coherence protocols with several network workloads on multicore processors.
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Size: 17806336 |
Author: pravin |
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Description: 分布式并行计算、分布式缓存、一致性、消息队列、分
布式文件系统为大型互联网云计算应用背后的核心技术
，是从业互联网云计算技术的工程师最关心和想掌握的
，目前广泛应用于搜索、云计算平台、大数据等领域.-Distributed parallel computing, distributed cache coherence, message queues, sub
Distributed file system for large-scale application of Internet cloud computing core technology behind
Is a practitioner of Internet cloud computing technology engineers are most concerned about and want to master
Field, now widely used in the search, cloud computing platform, big data
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Size: 9120768 |
Author: syf |
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Description: IOMMU enforces DMA cache coherence (ex. PCIe NoSnoop stripping). This capability is subject to change as groups are added or removed.
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Size: 7168 |
Author: kqhyner |
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